Lines Matching +full:tegra234 +full:- +full:xusb
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
27 In addition to per-lane configuration, USB 3.0 ports may require additional
28 settings on a per-board basis.
30 Pads will be represented as children of the top-level XUSB pad controller
33 PHY bindings, as described by the phy-bindings.txt file in this directory.
35 The Tegra hardware documentation refers to the connection between the XUSB
36 pad controller and the XUSB controller as "ports". This is confusing since
46 - nvidia,tegra194-xusb-padctl
47 - nvidia,tegra234-xusb-padctl
51 - description: pad controller registers
52 - description: AO registers
54 reg-names:
56 - const: padctl
57 - const: ao
61 - description: XUSB pad controller interrupt
65 - description: pad controller reset
67 reset-names:
69 - const: padctl
71 avdd-usb-supply:
72 description: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must
75 vclamp-usb-supply:
80 subnodes, one for each of the pads exposed by the XUSB pad controller.
97 - description: USB2 tracking clock
99 clock-names:
101 - const: trk
107 usb2-0:
111 "#phy-cells":
117 enum: [ xusb ]
119 usb2-1:
123 "#phy-cells":
129 enum: [ xusb ]
131 usb2-2:
135 "#phy-cells":
141 enum: [ xusb ]
143 usb2-3:
147 "#phy-cells":
153 enum: [ xusb ]
163 usb3-0:
167 "#phy-cells":
173 enum: [ xusb ]
175 usb3-1:
179 "#phy-cells":
185 enum: [ xusb ]
187 usb3-2:
191 "#phy-cells":
197 enum: [ xusb ]
199 usb3-3:
203 "#phy-cells":
209 enum: [ xusb ]
213 subnodes, one for each of the ports exposed by the XUSB pad controller.
223 usb2-0:
228 # match on gpio-usb-b-connector or usb-b-connector and cause
245 usb-role-switch:
252 See ../connector/usb-connector.yaml.
254 vbus-supply:
259 usb-role-switch: [ connector ]
261 usb2-1:
266 # match on gpio-usb-b-connector or usb-b-connector and cause
283 usb-role-switch:
290 See ../connector/usb-connector.yaml.
292 vbus-supply:
297 usb-role-switch: [ connector ]
299 usb2-2:
304 # match on gpio-usb-b-connector or usb-b-connector and cause
321 usb-role-switch:
328 See ../connector/usb-connector.yaml.
330 vbus-supply:
335 usb-role-switch: [ connector ]
337 usb2-3:
342 # match on gpio-usb-b-connector or usb-b-connector and cause
359 usb-role-switch:
366 See ../connector/usb-connector.yaml.
368 vbus-supply:
373 usb-role-switch: [ connector ]
375 usb3-0:
379 maximum-speed:
384 - description: The USB3 port supports USB 3.1 Gen 2 speed.
386 const: super-speed-plus
387 - description: The USB3 port supports USB 3.1 Gen 1 speed
389 const: super-speed
397 nvidia,usb2-companion:
399 number to map this super-speed USB port to. The range of
404 vbus-supply:
408 usb3-1:
412 maximum-speed:
417 - description: The USB3 port supports USB 3.1 Gen 2 speed.
419 const: super-speed-plus
420 - description: The USB3 port supports USB 3.1 Gen 1 speed
422 const: super-speed
430 nvidia,usb2-companion:
432 number to map this super-speed USB port to. The range of
437 vbus-supply:
441 usb3-2:
445 maximum-speed:
450 - description: The USB3 port supports USB 3.1 Gen 2 speed.
452 const: super-speed-plus
453 - description: The USB3 port supports USB 3.1 Gen 1 speed
455 const: super-speed
463 nvidia,usb2-companion:
465 number to map this super-speed USB port to. The range of
470 vbus-supply:
474 usb3-3:
478 maximum-speed:
483 - description: The USB3 port supports USB 3.1 Gen 2 speed.
485 const: super-speed-plus
486 - description: The USB3 port supports USB 3.1 Gen 1 speed
488 const: super-speed
496 nvidia,usb2-companion:
498 number to map this super-speed USB port to. The range of
503 vbus-supply:
510 - compatible
511 - reg
512 - resets
513 - reset-names
514 - avdd-usb-supply
515 - vclamp-usb-supply
518 - |
519 #include <dt-bindings/clock/tegra194-clock.h>
520 #include <dt-bindings/gpio/tegra194-gpio.h>
521 #include <dt-bindings/interrupt-controller/arm-gic.h>
522 #include <dt-bindings/reset/tegra194-reset.h>
525 compatible = "nvidia,tegra194-xusb-padctl";
528 reg-names = "padctl", "ao";
532 reset-names = "padctl";
534 avdd-usb-supply = <&vdd_usb_3v3>;
535 vclamp-usb-supply = <&vdd_1v8ao>;
540 clock-names = "trk";
543 usb2-0 {
544 nvidia,function = "xusb";
546 #phy-cells = <0>;
549 usb2-1 {
550 nvidia,function = "xusb";
551 #phy-cells = <0>;
554 usb2-2 {
555 nvidia,function = "xusb";
557 #phy-cells = <0>;
560 usb2-3 {
561 nvidia,function = "xusb";
562 #phy-cells = <0>;
569 usb3-0 {
570 nvidia,function = "xusb";
571 #phy-cells = <0>;
574 usb3-1 {
575 nvidia,function = "xusb";
577 #phy-cells = <0>;
580 usb3-2 {
581 nvidia,function = "xusb";
583 #phy-cells = <0>;
586 usb3-3 {
587 nvidia,function = "xusb";
588 #phy-cells = <0>;
595 usb2-0 {
599 usb2-1 {
600 vbus-supply = <&vdd_5v0_sys>;
604 usb2-2 {
608 usb2-3 {
609 vbus-supply = <&vdd_5v_sata>;
613 usb3-0 {
614 vbus-supply = <&vdd_5v0_sys>;
615 nvidia,usb2-companion = <1>;
618 usb3-1 {
622 usb3-2 {
626 usb3-3 {
627 maximum-speed = "super-speed";
628 vbus-supply = <&vdd_5v0_sys>;
629 nvidia,usb2-companion = <3>;