Lines Matching +full:xusb +full:- +full:padctl
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
27 In addition to per-lane configuration, USB 3.0 ports may require additional
28 settings on a per-board basis.
30 Pads will be represented as children of the top-level XUSB pad controller
33 PHY bindings, as described by the phy-bindings.txt file in this directory.
35 The Tegra hardware documentation refers to the connection between the XUSB
36 pad controller and the XUSB controller as "ports". This is confusing since
46 - enum:
47 - nvidia,tegra124-xusb-padctl
49 - items:
50 - const: nvidia,tegra132-xusb-padctl
51 - const: nvidia,tegra124-xusb-padctl
58 - description: XUSB pad controller interrupt
62 - description: pad controller reset
64 reset-names:
66 - const: padctl
68 avdd-pll-utmip-supply:
71 avdd-pll-erefe-supply:
74 avdd-pex-pll-supply:
77 hvdd-pex-pll-e-supply:
78 description: High-voltage PLLE power supply. Must supply 3.3 V.
82 subnodes, one for each of the pads exposed by the XUSB pad controller.
99 - description: USB2 tracking clock
101 clock-names:
103 - const: trk
109 usb2-0:
113 "#phy-cells":
119 enum: [ snps, xusb, uart ]
121 usb2-1:
125 "#phy-cells":
131 enum: [ snps, xusb, uart ]
133 usb2-2:
137 "#phy-cells":
143 enum: [ snps, xusb, uart ]
153 ulpi-0:
157 "#phy-cells":
163 enum: [ snps, xusb ]
171 - description: HSIC tracking clock
173 clock-names:
175 - const: trk
181 hsic-0:
185 "#phy-cells":
191 enum: [ snps, xusb ]
193 hsic-1:
197 "#phy-cells":
203 enum: [ snps, xusb ]
211 - description: PLLE clock
213 clock-names:
215 - const: pll
219 - description: reset for the PCIe UPHY block
221 reset-names:
223 - const: phy
229 pcie-0:
233 "#phy-cells":
239 enum: [ pcie, usb3-ss ]
241 pcie-1:
245 "#phy-cells":
251 enum: [ pcie, usb3-ss ]
253 pcie-2:
257 "#phy-cells":
263 enum: [ pcie, usb3-ss ]
265 pcie-3:
269 "#phy-cells":
275 enum: [ pcie, usb3-ss ]
277 pcie-4:
281 "#phy-cells":
287 enum: [ pcie, usb3-ss ]
295 - description: reset for the SATA UPHY block
297 reset-names:
299 - const: phy
305 sata-0:
309 "#phy-cells":
315 enum: [ sata, usb3-ss ]
319 subnodes, one for each of the ports exposed by the XUSB pad controller.
329 usb2-0:
334 # match on gpio-usb-b-connector or usb-b-connector and cause
351 usb-role-switch:
358 See ../connector/usb-connector.yaml.
360 vbus-supply:
364 usb2-1:
369 # match on gpio-usb-b-connector or usb-b-connector and cause
386 usb-role-switch:
393 See ../connector/usb-connector.yaml.
395 vbus-supply:
399 usb2-2:
404 # match on gpio-usb-b-connector or usb-b-connector and cause
421 usb-role-switch:
428 See ../connector/usb-connector.yaml.
430 vbus-supply:
434 ulpi-0:
444 vbus-supply:
448 hsic-0:
452 vbus-supply:
456 hsic-1:
460 vbus-supply:
464 usb3-0:
474 nvidia,usb2-companion:
476 number to map this super-speed USB port to. The range of
481 vbus-supply:
485 usb3-1:
495 nvidia,usb2-companion:
497 number to map this super-speed USB port to. The range of
502 vbus-supply:
509 - compatible
510 - reg
511 - resets
512 - reset-names
513 - avdd-pll-utmip-supply
514 - avdd-pll-erefe-supply
515 - avdd-pex-pll-supply
516 - hvdd-pex-pll-e-supply
520 - |
521 #include <dt-bindings/interrupt-controller/arm-gic.h>
523 padctl@7009f000 {
524 compatible = "nvidia,tegra124-xusb-padctl";
528 reset-names = "padctl";
530 avdd-pll-utmip-supply = <&vddio_1v8>;
531 avdd-pll-erefe-supply = <&avdd_1v05_run>;
532 avdd-pex-pll-supply = <&vdd_1v05_run>;
533 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
538 usb2-0 {
539 nvidia,function = "xusb";
540 #phy-cells = <0>;
543 usb2-1 {
544 nvidia,function = "xusb";
545 #phy-cells = <0>;
548 usb2-2 {
549 nvidia,function = "xusb";
550 #phy-cells = <0>;
557 ulpi-0 {
559 #phy-cells = <0>;
566 hsic-0 {
568 #phy-cells = <0>;
571 hsic-1 {
573 #phy-cells = <0>;
580 pcie-0 {
581 nvidia,function = "usb3-ss";
582 #phy-cells = <0>;
585 pcie-1 {
587 #phy-cells = <0>;
590 pcie-2 {
592 #phy-cells = <0>;
595 pcie-3 {
597 #phy-cells = <0>;
600 pcie-4 {
602 #phy-cells = <0>;
609 sata-0 {
611 #phy-cells = <0>;
619 usb2-0 {
624 usb2-1 {
629 usb2-2 {
630 vbus-supply = <&vdd_usb3_vbus>;
634 ulpi-0 {
638 hsic-0 {
642 hsic-1 {
646 usb3-0 {
647 nvidia,usb2-companion = <2>;
650 usb3-1 {