Lines Matching +full:ports +full:- +full:lane +full:- +full:control
5 signals) which connect directly to pins/pads on the SoC package. Each lane
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
21 device tree node. Each lane exposed by the pad will be represented by its
22 own subnode and can be referenced by users of the lane using the standard
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
26 pad controller and the XUSB controller as "ports". This is confusing since
34 --------------------
35 - compatible: Must be:
36 - Tegra124: "nvidia,tegra124-xusb-padctl"
37 - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
38 - Tegra210: "nvidia,tegra210-xusb-padctl"
39 - Tegra186: "nvidia,tegra186-xusb-padctl"
40 - Tegra194: "nvidia,tegra194-xusb-padctl"
41 - reg: Physical base address and length of the controller's registers.
42 - resets: Must contain an entry for each entry in reset-names.
43 - reset-names: Must include the following entries:
44 - "padctl"
47 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
48 - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
49 - avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
50 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
53 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
54 - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
55 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
56 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
57 - nvidia,pmc: phandle and specifier referring to the Tegra210 PMC node.
60 - avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
62 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
64 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
65 - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
68 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
70 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
90 ---------
93 - clocks: Must contain an entry for each entry in clock-names.
94 - clock-names: Must contain the following entries:
95 - "trk": phandle and specifier referring to the USB2 tracking clock
98 ---------
101 - clocks: Must contain an entry for each entry in clock-names.
102 - clock-names: Must contain the following entries:
103 - "trk": phandle and specifier referring to the HSIC tracking clock
106 ---------
109 - clocks: Must contain an entry for each entry in clock-names.
110 - clock-names: Must contain the following entries:
111 - "pll": phandle and specifier referring to the PLLE
112 - resets: Must contain an entry for each entry in reset-names.
113 - reset-names: Must contain the following entries:
114 - "phy": reset for the PCIe UPHY block
117 ---------
120 - resets: Must contain an entry for each entry in reset-names.
121 - reset-names: Must contain the following entries:
122 - "phy": reset for the SATA UPHY block
132 --------------------
133 - status: Defines the operation status of the PHY. Valid values are:
134 - "disabled": the PHY is disabled
135 - "okay": the PHY is enabled
136 - #phy-cells: Should be 0. Since each lane represents a single PHY, there is
138 - nvidia,function: The output function of the PHY. See below for a list of
142 - usb2: usb2-0, usb2-1, usb2-2
143 - functions: "snps", "xusb", "uart"
144 - ulpi: ulpi-0
145 - functions: "snps", "xusb"
146 - hsic: hsic-0, hsic-1
147 - functions: "snps", "xusb"
148 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
149 - functions: "pcie", "usb3-ss"
150 - sata: sata-0
151 - functions: "usb3-ss", "sata"
154 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
155 - functions: "snps", "xusb", "uart"
156 - hsic: hsic-0, hsic-1
157 - functions: "snps", "xusb"
158 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
159 - functions: "pcie-x1", "usb3-ss", "pcie-x4"
160 - sata: sata-0
161 - functions: "usb3-ss", "sata"
164 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
165 - functions: "xusb"
166 - usb3: usb3-0, usb3-1, usb3-2, usb3-3
167 - functions: "xusb"
172 A required child node named "ports" contains a list of all the ports exposed
173 by the XUSB pad controller. Per-port configuration is only required for USB.
175 USB2 ports:
176 -----------
179 - status: Defines the operation status of the port. Valid values are:
180 - "disabled": the port is disabled
181 - "okay": the port is enabled
182 - mode: A string that determines the mode in which to run the port. Valid
184 - "host": for USB host mode
185 - "device": for USB device mode
186 - "otg": for USB OTG mode
188 Required properties for OTG/Peripheral capable USB2 ports:
189 - usb-role-switch: Boolean property to indicate that the port support OTG or
192 See usb/usb-conn-gpio.txt.
195 - nvidia,internal: A boolean property whose presence determines that a port
198 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
200 ULPI ports:
201 -----------
204 - status: Defines the operation status of the port. Valid values are:
205 - "disabled": the port is disabled
206 - "okay": the port is enabled
207 - nvidia,internal: A boolean property whose presence determines that a port
210 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
212 HSIC ports:
213 -----------
216 - status: Defines the operation status of the port. Valid values are:
217 - "disabled": the port is disabled
218 - "okay": the port is enabled
221 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
223 Super-speed USB ports:
224 ----------------------
227 - status: Defines the operation status of the port. Valid values are:
228 - "disabled": the port is disabled
229 - "okay": the port is enabled
230 - nvidia,usb2-companion: A single cell that specifies the physical port number
231 to map this super-speed USB port to. The range of valid port numbers varies
233 - 0-2: for Tegra124 and Tegra132
234 - 0-3: for Tegra210
237 - nvidia,internal: A boolean property whose presence determines that a port
241 - maximum-speed: Only for Tegra194. A string property that specifies maximum
243 - "super-speed-plus": default, the usb3 port supports USB 3.1 Gen 2 speed.
244 - "super-speed": the usb3 port supports USB 3.1 Gen 1 speed only.
247 ports:
248 - 3x USB2: usb2-0, usb2-1, usb2-2
249 - 1x ULPI: ulpi-0
250 - 2x HSIC: hsic-0, hsic-1
251 - 2x super-speed USB: usb3-0, usb3-1
253 For Tegra210, the XUSB pad controller exposes the following ports:
254 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
255 - 2x HSIC: hsic-0, hsic-1
256 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
258 For Tegra194, the XUSB pad controller exposes the following ports:
259 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
260 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
266 ----------------------
272 compatible = "nvidia,tegra124-xusb-padctl";
274 compatible = "nvidia,tegra132-xusb-padctl",
275 "nvidia,tegra124-xusb-padctl";
278 reset-names = "padctl";
285 usb2-0 {
287 #phy-cells = <0>;
290 usb2-1 {
292 #phy-cells = <0>;
295 usb2-2 {
297 #phy-cells = <0>;
306 ulpi-0 {
308 #phy-cells = <0>;
317 hsic-0 {
319 #phy-cells = <0>;
322 hsic-1 {
324 #phy-cells = <0>;
333 pcie-0 {
335 #phy-cells = <0>;
338 pcie-1 {
340 #phy-cells = <0>;
343 pcie-2 {
345 #phy-cells = <0>;
348 pcie-3 {
350 #phy-cells = <0>;
353 pcie-4 {
355 #phy-cells = <0>;
364 sata-0 {
366 #phy-cells = <0>;
372 ports {
373 usb2-0 {
377 usb2-1 {
381 usb2-2 {
385 ulpi-0 {
389 hsic-0 {
393 hsic-1 {
397 usb3-0 {
401 usb3-1 {
417 usb2-0 {
422 usb2-1 {
427 usb2-2 {
438 pcie-0 {
439 nvidia,function = "usb3-ss";
443 pcie-2 {
448 pcie-4 {
459 sata-0 {
467 ports {
469 usb2-0 {
475 usb2-1 {
481 usb2-2 {
485 vbus-supply = <&vdd_usb3_vbus>;
488 usb3-0 {
496 ---------
501 compatible = "nvidia,tegra210-xusb-padctl";
504 reset-names = "padctl";
511 clock-names = "trk";
515 usb2-0 {
517 #phy-cells = <0>;
520 usb2-1 {
522 #phy-cells = <0>;
525 usb2-2 {
527 #phy-cells = <0>;
530 usb2-3 {
532 #phy-cells = <0>;
539 clock-names = "trk";
543 hsic-0 {
545 #phy-cells = <0>;
548 hsic-1 {
550 #phy-cells = <0>;
557 clock-names = "pll";
559 reset-names = "phy";
563 pcie-0 {
565 #phy-cells = <0>;
568 pcie-1 {
570 #phy-cells = <0>;
573 pcie-2 {
575 #phy-cells = <0>;
578 pcie-3 {
580 #phy-cells = <0>;
583 pcie-4 {
585 #phy-cells = <0>;
588 pcie-5 {
590 #phy-cells = <0>;
593 pcie-6 {
595 #phy-cells = <0>;
602 clock-names = "pll";
604 reset-names = "phy";
608 sata-0 {
610 #phy-cells = <0>;
616 ports {
617 usb2-0 {
621 usb2-1 {
625 usb2-2 {
629 usb2-3 {
633 hsic-0 {
637 hsic-1 {
641 usb3-0 {
645 usb3-1 {
649 usb3-2 {
653 usb3-3 {
669 usb2-0 {
674 usb2-1 {
679 usb2-2 {
684 usb2-3 {
695 pcie-0 {
696 nvidia,function = "pcie-x1";
700 pcie-1 {
701 nvidia,function = "pcie-x4";
705 pcie-2 {
706 nvidia,function = "pcie-x4";
710 pcie-3 {
711 nvidia,function = "pcie-x4";
715 pcie-4 {
716 nvidia,function = "pcie-x4";
720 pcie-5 {
721 nvidia,function = "usb3-ss";
725 pcie-6 {
726 nvidia,function = "usb3-ss";
736 sata-0 {
744 ports {
745 usb2-0 {
750 usb2-1 {
752 vbus-supply = <&vdd_5v0_rtl>;
756 usb2-2 {
758 vbus-supply = <&vdd_usb_vbus>;
762 usb2-3 {
767 usb3-0 {
769 nvidia,lanes = "pcie-6";
773 usb3-1 {
775 nvidia,lanes = "pcie-5";