Lines Matching +full:imx8qxp +full:- +full:mipi +full:- +full:dphy

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Guido Günther <agx@sigxcpu.org>
13   The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14   MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
18   in either MIPI-DSI PHY mode or LVDS PHY mode.
23       - fsl,imx8mq-mipi-dphy
24       - fsl,imx8qxp-mipi-dphy
32   clock-names:
35   "#phy-cells":
43   power-domains:
47   - compatible
48   - reg
49   - clocks
50   - clock-names
51   - "#phy-cells"
52   - power-domains
55   - if:
59             const: fsl,imx8mq-mipi-dphy
65         - assigned-clocks
66         - assigned-clock-parents
67         - assigned-clock-rates
69   - if:
73             const: fsl,imx8qxp-mipi-dphy
76         assigned-clocks: false
77         assigned-clock-parents: false
78         assigned-clock-rates: false
81         - fsl,syscon
86   - |
87     #include <dt-bindings/clock/imx8mq-clock.h>
88     dphy: dphy@30a0030 {
89         compatible = "fsl,imx8mq-mipi-dphy";
92         clock-names = "phy_ref";
93         assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
94         assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
95         assigned-clock-rates = <24000000>;
96         #phy-cells = <0>;
97         power-domains = <&pgc_mipi>;