Lines Matching +full:imx8mq +full:- +full:clock

3 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
4 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
8 - compatible: Must be:
9   - "fsl,imx8mq-mipi-dphy"
10 - clocks: Must contain an entry for each entry in clock-names.
11 - clock-names: Must contain the following entries:
12   - "phy_ref": phandle and specifier referring to the DPHY ref clock
13 - reg: the register range of the PHY controller
14 - #phy-cells: number of cells in PHY, as defined in
15   Documentation/devicetree/bindings/phy/phy-bindings.txt
19 - power-domains: phandle to power domain
23 		compatible = "fsl,imx8mq-mipi-dphy";
25 		clock-names = "phy_ref";
27 		power-domains = <&pd_mipi0>;
28 		#phy-cells = <0>;