Lines Matching +full:phy +full:- +full:ref +full:- +full:clk
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
45 pattern: "^xs-phy@[0-9a-f]+$"
49 - enum:
50 - mediatek,mt3611-xsphy
51 - mediatek,mt3612-xsphy
52 - const: mediatek,xsphy
60 "#address-cells":
63 "#size-cells":
68 mediatek,src-ref-clk-mhz:
73 mediatek,src-coef:
76 $ref: /schemas/types.yaml#/definitions/uint32
81 "^usb-phy@[0-9a-f]+$":
84 A sub-node is required for each port the controller provides.
94 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
96 clock-names:
98 - const: ref
100 "#phy-cells":
105 - description: The PHY type
107 - PHY_TYPE_USB2
108 - PHY_TYPE_USB3
111 mediatek,eye-src:
113 The value of slew rate calibrate (U2 phy)
114 $ref: /schemas/types.yaml#/definitions/uint32
118 mediatek,eye-vrt:
120 The selection of VRT reference voltage (U2 phy)
121 $ref: /schemas/types.yaml#/definitions/uint32
125 mediatek,eye-term:
127 The selection of HS_TX TERM reference voltage (U2 phy)
128 $ref: /schemas/types.yaml#/definitions/uint32
132 mediatek,efuse-intr:
134 The selection of Internal Resistor (U2/U3 phy)
135 $ref: /schemas/types.yaml#/definitions/uint32
139 mediatek,efuse-tx-imp:
141 The selection of TX Impedance (U3 phy)
142 $ref: /schemas/types.yaml#/definitions/uint32
146 mediatek,efuse-rx-imp:
148 The selection of RX Impedance (U3 phy)
149 $ref: /schemas/types.yaml#/definitions/uint32
154 - reg
155 - clocks
156 - clock-names
157 - "#phy-cells"
162 - compatible
163 - "#address-cells"
164 - "#size-cells"
165 - ranges
170 - |
171 #include <dt-bindings/phy/phy.h>
173 u3phy: xs-phy@11c40000 {
174 compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
176 mediatek,src-ref-clk-mhz = <26>;
177 mediatek,src-coef = <17>;
178 #address-cells = <1>;
179 #size-cells = <1>;
182 u2port0: usb-phy@11c40000 {
185 clock-names = "ref";
186 mediatek,eye-src = <4>;
187 #phy-cells = <1>;
190 u3port0: usb-phy@11c43000 {
193 clock-names = "ref";
194 mediatek,efuse-intr = <28>;
195 #phy-cells = <1>;