Lines Matching +full:syscon +full:- +full:phy +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy(@[0-9a-f]+)?$"
71 - items:
72 - enum:
73 - mediatek,mt2701-tphy
74 - mediatek,mt7623-tphy
75 - mediatek,mt7622-tphy
76 - mediatek,mt8516-tphy
77 - const: mediatek,generic-tphy-v1
78 - items:
79 - enum:
80 - mediatek,mt2712-tphy
81 - mediatek,mt6893-tphy
82 - mediatek,mt7629-tphy
83 - mediatek,mt7986-tphy
84 - mediatek,mt8183-tphy
85 - mediatek,mt8186-tphy
86 - mediatek,mt8192-tphy
87 - mediatek,mt8365-tphy
88 - const: mediatek,generic-tphy-v2
89 - items:
90 - enum:
91 - mediatek,mt8188-tphy
92 - mediatek,mt8195-tphy
93 - const: mediatek,generic-tphy-v3
94 - const: mediatek,mt2701-u3phy
96 - const: mediatek,mt2712-u3phy
98 - const: mediatek,mt8173-u3phy
103 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
104 T-PHY V2/V3, such as mt2712.
107 "#address-cells":
110 "#size-cells":
113 # Used with non-empty value if optional 'reg' is not provided.
115 # (child-bus-address, parent-bus-address, length).
118 mediatek,src-ref-clk-mhz:
123 mediatek,src-coef:
129 power-domains:
141 "^(usb|pcie|sata)-phy@[0-9a-f]+$":
144 A sub-node is required for each port the controller provides.
155 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
156 - description: Reference clock of analog phy
161 clock-names:
164 - const: ref
165 - const: da_ref
167 "#phy-cells":
172 - description: The PHY type
174 - PHY_TYPE_USB2
175 - PHY_TYPE_USB3
176 - PHY_TYPE_PCIE
177 - PHY_TYPE_SATA
178 - PHY_TYPE_SGMII
180 nvmem-cells:
182 - description: internal R efuse for U2 PHY or U3/PCIe PHY
183 - description: rx_imp_sel efuse for U3/PCIe PHY
184 - description: tx_imp_sel efuse for U3/PCIe PHY
187 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these
188 three items should be provided at the same time for U3/PCIe PHY,
190 If unspecified, will use hardware auto-load efuse.
192 nvmem-cell-names:
194 - const: intr
195 - const: rx_imp
196 - const: tx_imp
199 mediatek,eye-src:
201 The value of slew rate calibrate (U2 phy)
206 mediatek,eye-vrt:
208 The selection of VRT reference voltage (U2 phy)
213 mediatek,eye-term:
215 The selection of HS_TX TERM reference voltage (U2 phy)
222 The selection of internal resistor (U2 phy)
229 The selection of disconnect threshold (U2 phy)
234 mediatek,pre-emphasis:
236 The level of pre-emphasis which used to widen the eye opening and
239 8.3% etc. (U2 phy)
249 mediatek,force-mode:
251 The force mode is used to manually switch the shared phy mode between
252 USB3 and PCIe, when USB3 phy type is selected by the consumer, and
253 force-mode is set, will cause phy's power and pipe toggled and force
254 phy as USB3 mode which switched from default PCIe mode. But prefer to
255 use the property "mediatek,syscon-type" for newer SoCs that support it.
258 mediatek,syscon-type:
259 $ref: /schemas/types.yaml#/definitions/phandle-array
262 A phandle to syscon used to access the register of type switch,
266 - description:
267 The first cell represents a phandle to syscon
268 - description:
270 - description:
275 - reg
276 - "#phy-cells"
281 - compatible
282 - "#address-cells"
283 - "#size-cells"
284 - ranges
289 - |
290 #include <dt-bindings/clock/mt8173-clk.h>
291 #include <dt-bindings/interrupt-controller/arm-gic.h>
292 #include <dt-bindings/interrupt-controller/irq.h>
293 #include <dt-bindings/phy/phy.h>
295 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
297 reg-names = "mac", "ippc";
303 clock-names = "sys_ck";
306 t-phy@11290000 {
307 compatible = "mediatek,mt8173-u3phy";
309 #address-cells = <1>;
310 #size-cells = <1>;
313 u2port0: usb-phy@11290800 {
316 clock-names = "ref", "da_ref";
317 #phy-cells = <1>;
320 u3port0: usb-phy@11290900 {
323 clock-names = "ref";
324 #phy-cells = <1>;
327 u2port1: usb-phy@11291000 {
329 #phy-cells = <1>;