Lines Matching +full:otg +full:- +full:vbus
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-a83t-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU1 registers
24 - description: PHY PMU2 registers
26 reg-names:
28 - const: phy_ctrl
29 - const: pmu1
30 - const: pmu2
34 - description: USB OTG PHY bus clock
35 - description: USB Host 0 PHY bus clock
36 - description: USB Host 1 PHY bus clock
37 - description: USB HSIC 12MHz clock
39 clock-names:
41 - const: usb0_phy
42 - const: usb1_phy
43 - const: usb2_phy
44 - const: usb2_hsic_12M
48 - description: USB OTG reset
49 - description: USB Host 1 Controller reset
50 - description: USB Host 2 Controller reset
52 reset-names:
54 - const: usb0_reset
55 - const: usb1_reset
56 - const: usb2_reset
58 usb0_id_det-gpios:
60 description: GPIO to the USB OTG ID pin
62 usb0_vbus_det-gpios:
64 description: GPIO to the USB OTG VBUS detect pin
66 usb0_vbus_power-supply:
67 description: Power supply to detect the USB OTG VBUS
69 usb0_vbus-supply:
70 description: Regulator controlling USB OTG VBUS
72 usb1_vbus-supply:
75 usb2_vbus-supply:
79 - "#phy-cells"
80 - compatible
81 - clocks
82 - clock-names
83 - reg
84 - reg-names
85 - resets
86 - reset-names
91 - |
92 #include <dt-bindings/gpio/gpio.h>
93 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
94 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
97 #phy-cells = <1>;
98 compatible = "allwinner,sun8i-a83t-usb-phy";
102 reg-names = "phy_ctrl",
109 clock-names = "usb0_phy",
116 reset-names = "usb0_reset",
119 usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
120 usb0_vbus_power-supply = <&usb_power_supply>;
121 usb0_vbus-supply = <®_drivevbus>;
122 usb1_vbus-supply = <®_usb1_vbus>;
123 usb2_vbus-supply = <®_usb2_vbus>;