Lines Matching +full:axi +full:- +full:ports

1 * Xilinx AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9 - reg: Should contain AXI PCIe registers location and length
10 - device_type: must be "pci"
11 - interrupts: Should contain AXI PCIe interrupt
12 - interrupt-map-mask,
13   interrupt-map: standard PCI properties to define the mapping of the
15 - ranges: ranges for the PCI memory regions (I/O space region is not
21 - bus-range: PCI bus numbers covered
26 - interrupt-controller: identifies the node as an interrupt controller
27 - #address-cells: specifies the number of cells needed to encode an
29 - #interrupt-cells: specifies the number of cells needed to encode an
34 created a interrupt controller node to support 'interrupt-map' DT
42 	pci_express: axi-pcie@50000000 {
43 		#address-cells = <3>;
44 		#size-cells = <2>;
45 		#interrupt-cells = <1>;
46 		compatible = "xlnx,axi-pcie-host-1.00.a";
50 		interrupt-map-mask = <0 0 0 7>;
51 		interrupt-map = <0 0 0 1 &pcie_intc 1>,
57 		pcie_intc: interrupt-controller {
58 			interrupt-controller;
59 			#address-cells = <0>;
60 			#interrupt-cells = <1>;
66 	pci_express: axi-pcie@10000000 {
67 		#address-cells = <3>;
68 		#size-cells = <2>;
69 		#interrupt-cells = <1>;
70 		compatible = "xlnx,axi-pcie-host-1.00.a";
73 		interrupt-parent = <&microblaze_0_intc>;
75 		interrupt-map-mask = <0 0 0 7>;
76 		interrupt-map = <0 0 0 1 &pcie_intc 1>,
82 		pcie_intc: interrupt-controller {
83 			interrupt-controller;
84 			#address-cells = <0>;
85 			#interrupt-cells = <1>;