Lines Matching +full:syscon +full:- +full:pcie +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - const: ti,j721e-pcie-host
17 - const: ti,j784s4-pcie-host
18 - description: PCIe controller in AM64
20 - const: ti,am64-pcie-host
21 - const: ti,j721e-pcie-host
22 - description: PCIe controller in J7200
24 - const: ti,j7200-pcie-host
25 - const: ti,j721e-pcie-host
30 reg-names:
32 - const: intd_cfg
33 - const: user_cfg
34 - const: reg
35 - const: cfg
37 ti,syscon-pcie-ctrl:
38 $ref: /schemas/types.yaml#/definitions/phandle-array
40 - items:
41 - description: Phandle to the SYSCON entry
42 - description: pcie_ctrl register offset within SYSCON
43 description: Specifier for configuring PCIe mode and link speed.
45 power-domains:
52 clock-specifier to represent input to the PCIe for 1 item.
55 clock-names:
58 - const: fck
59 - const: pcie_refclk
61 dma-coherent: true
63 vendor-id:
66 device-id:
68 - 0xb00d
69 - 0xb00f
70 - 0xb010
71 - 0xb013
73 msi-map: true
78 interrupt-names:
80 - const: link_state
82 interrupt-controller:
87 interrupt-controller: true
89 '#interrupt-cells':
96 - $ref: cdns-pcie-host.yaml#
97 - if:
101 - ti,am64-pcie-host
104 num-lanes:
107 - if:
111 - ti,j7200-pcie-host
112 - ti,j721e-pcie-host
115 num-lanes:
119 - if:
123 - ti,j784s4-pcie-host
126 num-lanes:
131 - compatible
132 - reg
133 - reg-names
134 - ti,syscon-pcie-ctrl
135 - max-link-speed
136 - num-lanes
137 - power-domains
138 - clocks
139 - clock-names
140 - vendor-id
141 - device-id
142 - msi-map
143 - dma-ranges
144 - ranges
145 - reset-gpios
146 - phys
147 - phy-names
152 - |
153 #include <dt-bindings/soc/ti,sci_pm_domain.h>
154 #include <dt-bindings/gpio/gpio.h>
157 #address-cells = <2>;
158 #size-cells = <2>;
160 pcie0_rc: pcie@2900000 {
161 compatible = "ti,j721e-pcie-host";
166 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
167 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
168 max-link-speed = <3>;
169 num-lanes = <2>;
170 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
172 clock-names = "fck";
174 #address-cells = <3>;
175 #size-cells = <2>;
176 bus-range = <0x0 0xf>;
177 vendor-id = <0x104c>;
178 device-id = <0xb00d>;
179 msi-map = <0x0 &gic_its 0x0 0x10000>;
180 dma-coherent;
181 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
183 phy-names = "pcie-phy";
186 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;