Lines Matching +full:pcie +full:- +full:ob
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
22 - socionext,uniphier-nx1-pcie-ep
28 reg-names:
31 - const: dbi
32 - const: dbi2
33 - const: link
34 - const: addr_space
35 - const: atu
41 clock-names: true
47 reset-names: true
49 num-ib-windows:
52 num-ob-windows:
55 num-lanes: true
60 phy-names:
61 const: pcie-phy
64 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
65 - if:
69 const: socionext,uniphier-pro5-pcie-ep
74 reg-names:
78 clock-names:
80 - const: gio
81 - const: link
84 reset-names:
86 - const: gio
87 - const: link
92 reg-names:
96 clock-names:
100 reset-names:
104 - compatible
105 - reg
106 - reg-names
107 - clocks
108 - clock-names
109 - resets
110 - reset-names
115 - |
116 pcie_ep: pcie-ep@66000000 {
117 compatible = "socionext,uniphier-pro5-pcie-ep";
118 reg-names = "dbi", "dbi2", "link", "addr_space";
121 clock-names = "gio", "link";
123 reset-names = "gio", "link";
125 num-ib-windows = <16>;
126 num-ob-windows = <16>;
127 num-lanes = <4>;
128 phy-names = "pcie-phy";