Lines Matching full:description
13 description:
21 description:
43 description:
62 description:
76 - description:
81 - description:
85 - description:
89 - description:
93 - description:
97 - description:
102 - description:
108 - description:
113 - description:
117 - description: See native 'dbi' clock for details
119 - description: See native 'mstr/slv' clock for details
121 - description: See native 'pipe' clock for details
123 - description: See native 'aux' clock for details
125 - description: See native 'ref' clock for details.
127 - description: See nativs 'phy_reg' clock for details
131 description:
147 - description: Data Bus Interface (DBI) domain reset
149 - description: AXI-bus Master interface reset
151 - description: AXI-bus Slave interface reset
153 - description: Application-dependent interface reset
155 - description: Controller Non-sticky CSR flags reset
157 - description: Controller sticky CSR flags reset
159 - description: PIPE-interface (Core-PCS) logic reset
161 - description:
164 - description: PCS/PHY block reset
166 - description: PMC hot reset signal
168 - description: Cold reset signal
170 - description:
174 - description: See native 'app' reset for details
176 - description: See native 'phy' reset for details
178 - description: See native 'pwr' reset for details
182 description:
194 - description: Generic PHY names
197 - description:
207 description:
213 description:
222 description:
230 description:
239 description:
249 description:
256 description: