Lines Matching +full:pcie +full:- +full:phy +full:- +full:0
1 * Rockchip AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names: Must include the following entries:
16 - "aclk"
17 - "aclk-perf"
18 - "hclk"
19 - "pm"
20 - msi-map: Maps a Requester ID to an MSI controller and associated
21 msi-specifier data. See ./pci-msi.txt
22 - interrupts: Three interrupt entries must be specified.
23 - interrupt-names: Must include the following names
24 - "sys"
25 - "legacy"
26 - "client"
27 - resets: Must contain seven entries for each entry in reset-names.
29 - reset-names: Must include the following names
30 - "core"
31 - "mgmt"
32 - "mgmt-sticky"
33 - "pipe"
34 - "pm"
35 - "aclk"
36 - "pclk"
37 - pinctrl-names : The pin control state names
38 - pinctrl-0: The "default" pinctrl state
39 - #interrupt-cells: specifies the number of cells needed to encode an
41 - interrupt-map-mask and interrupt-map: standard PCI properties
43 Required properties for legacy PHY model (deprecated):
44 - phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
45 - phy-names: MUST be "pcie-phy".
47 Required properties for per-lane PHY model (preferred):
48 - phys: Must contain an phandle to a PHY for each entry in phy-names.
49 - phy-names: Must include 4 entries for all 4 lanes even if some of
50 them won't be used for your cases. Entries are of the form "pcie-phy-N":
51 where N ranges from 0 to 3.
52 (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
53 for changing the #phy-cells of phy node to support it)
56 - aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
57 using 24MHz OSC for RC's PHY.
58 - ep-gpios: contain the entry for pre-reset GPIO
59 - num-lanes: number of lanes to use
60 - vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
61 - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
62 - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
63 - vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
66 The core controller provides a single interrupt for legacy INTx. The PCIe node
68 'interrupt-map' property. This node represents the domain at which the four
73 - interrupt-controller: identifies the node as an interrupt controller
74 - #address-cells: specifies the number of cells needed to encode an
75 address. The value must be 0.
76 - #interrupt-cells: specifies the number of cells needed to encode an
81 pcie0: pcie@f8000000 {
82 compatible = "rockchip,rk3399-pcie";
83 #address-cells = <3>;
84 #size-cells = <2>;
87 clock-names = "aclk", "aclk-perf",
89 bus-range = <0x0 0x1>;
90 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
91 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
92 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
93 interrupt-names = "sys", "legacy", "client";
94 assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
95 assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
96 assigned-clock-rates = <100000000>;
97 ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
98 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
99 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
100 num-lanes = <4>;
101 msi-map = <0x0 &its 0x0 0x1000>;
102 reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
103 reg-names = "axi-base", "apb-base";
107 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
109 /* deprecated legacy PHY model */
111 phy-names = "pcie-phy";
112 pinctrl-names = "default";
113 pinctrl-0 = <&pcie_clkreq>;
114 #interrupt-cells = <1>;
115 interrupt-map-mask = <0 0 0 7>;
116 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
117 <0 0 0 2 &pcie0_intc 1>,
118 <0 0 0 3 &pcie0_intc 2>,
119 <0 0 0 4 &pcie0_intc 3>;
120 pcie0_intc: interrupt-controller {
121 interrupt-controller;
122 #address-cells = <0>;
123 #interrupt-cells = <1>;
127 pcie0: pcie@f8000000 {
130 /* preferred per-lane PHY model */
131 phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
132 phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";