Lines Matching +full:aux +full:- +full:gpios
3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sc8180x" for sc8180x
16 - "qcom,pcie-sdm845" for sdm845
17 - "qcom,pcie-sm8250" for sm8250
18 - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450
19 - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450
20 - "qcom,pcie-ipq6018" for ipq6018
22 - reg:
24 Value type: <prop-encoded-array>
25 Definition: Register ranges as listed in the reg-names property
27 - reg-names:
31 - "parf" Qualcomm specific registers
32 - "dbi" DesignWare PCIe registers
33 - "elbi" External local bus interface registers
34 - "config" PCIe configuration space
35 - "atu" ATU address space (optional)
37 - device_type:
40 Definition: Should be "pci". As specified in snps,dw-pcie.yaml
42 - #address-cells:
45 Definition: Should be 3. As specified in snps,dw-pcie.yaml
47 - #size-cells:
50 Definition: Should be 2. As specified in snps,dw-pcie.yaml
52 - ranges:
54 Value type: <prop-encoded-array>
55 Definition: As specified in snps,dw-pcie.yaml
57 - interrupts:
59 Value type: <prop-encoded-array>
62 - interrupt-names:
67 - #interrupt-cells:
70 Definition: Should be 1. As specified in snps,dw-pcie.yaml
72 - interrupt-map-mask:
74 Value type: <prop-encoded-array>
75 Definition: As specified in snps,dw-pcie.yaml
77 - interrupt-map:
79 Value type: <prop-encoded-array>
80 Definition: As specified in snps,dw-pcie.yaml
82 - clocks:
84 Value type: <prop-encoded-array>
86 in clock-names property
88 - clock-names:
92 - "iface" Configuration AHB clock
94 - clock-names:
98 - "core" Clocks the pcie hw block
99 - "phy" Clocks the pcie PHY block
100 - "aux" Clocks the pcie AUX block
101 - "ref" Clocks the pcie ref block
102 - clock-names:
106 - "aux" Auxiliary (AUX) clock
107 - "bus_master" Master AXI clock
108 - "bus_slave" Slave AXI clock
110 - clock-names:
114 - "pipe" Pipe Clock driving internal logic
115 - "aux" Auxiliary (AUX) clock
116 - "cfg" Configuration clock
117 - "bus_master" Master AXI clock
118 - "bus_slave" Slave AXI clock
120 - clock-names:
124 - "iface" PCIe to SysNOC BIU clock
125 - "axi_m" AXI Master clock
126 - "axi_s" AXI Slave clock
127 - "ahb" AHB clock
128 - "aux" Auxiliary clock
130 - clock-names:
134 - "iface" PCIe to SysNOC BIU clock
135 - "axi_m" AXI Master clock
136 - "axi_s" AXI Slave clock
137 - "axi_bridge" AXI bridge clock
138 - "rchng"
140 - clock-names:
144 - "iface" AHB clock
145 - "aux" Auxiliary clock
146 - "master_bus" AXI Master clock
147 - "slave_bus" AXI Slave clock
149 - clock-names:
153 - "aux" Auxiliary clock
154 - "cfg" Configuration clock
155 - "bus_master" Master AXI clock
156 - "bus_slave" Slave AXI clock
157 - "slave_q2a" Slave Q2A clock
158 - "tbu" PCIe TBU clock
159 - "pipe" PIPE clock
161 - clock-names:
165 - "aux" Auxiliary clock
166 - "cfg" Configuration clock
167 - "bus_master" Master AXI clock
168 - "bus_slave" Slave AXI clock
169 - "slave_q2a" Slave Q2A clock
170 - "tbu" PCIe TBU clock
171 - "ddrss_sf_tbu" PCIe SF TBU clock
172 - "pipe" PIPE clock
174 - clock-names:
175 Usage: required for sm8450-pcie0 and sm8450-pcie1
178 - "aux" Auxiliary clock
179 - "cfg" Configuration clock
180 - "bus_master" Master AXI clock
181 - "bus_slave" Slave AXI clock
182 - "slave_q2a" Slave Q2A clock
183 - "tbu" PCIe TBU clock
184 - "ddrss_sf_tbu" PCIe SF TBU clock
185 - "pipe" PIPE clock
186 - "pipe_mux" PIPE MUX
187 - "phy_pipe" PIPE output clock
188 - "ref" REFERENCE clock
189 - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0
190 - "aggre1" Aggre NoC PCIe1 AXI clock
192 - resets:
194 Value type: <prop-encoded-array>
196 in reset-names property
198 - reset-names:
202 - "axi" AXI reset
203 - "ahb" AHB reset
204 - "por" POR reset
205 - "pci" PCI reset
206 - "phy" PHY reset
208 - reset-names:
212 - "core" Core reset
214 - reset-names:
218 - "axi_m" AXI master reset
219 - "axi_s" AXI slave reset
220 - "pipe" PIPE reset
221 - "axi_m_vmid" VMID reset
222 - "axi_s_xpu" XPU reset
223 - "parf" PARF reset
224 - "phy" PHY reset
225 - "axi_m_sticky" AXI sticky reset
226 - "pipe_sticky" PIPE sticky reset
227 - "pwr" PWR reset
228 - "ahb" AHB reset
229 - "phy_ahb" PHY AHB reset
230 - "ext" EXT reset
232 - reset-names:
236 - "pipe" PIPE reset
237 - "sleep" Sleep reset
238 - "sticky" Core Sticky reset
239 - "axi_m" AXI Master reset
240 - "axi_s" AXI Slave reset
241 - "ahb" AHB Reset
242 - "axi_m_sticky" AXI Master Sticky reset
244 - reset-names:
248 - "pipe" PIPE reset
249 - "sleep" Sleep reset
250 - "sticky" Core Sticky reset
251 - "axi_m" AXI Master reset
252 - "axi_s" AXI Slave reset
253 - "ahb" AHB Reset
254 - "axi_m_sticky" AXI Master Sticky reset
255 - "axi_s_sticky" AXI Slave Sticky reset
257 - reset-names:
261 - "axi_m" AXI Master reset
262 - "axi_s" AXI Slave reset
263 - "axi_m_sticky" AXI Master Sticky reset
264 - "pipe_sticky" PIPE sticky reset
265 - "pwr" PWR reset
266 - "ahb" AHB reset
268 - reset-names:
272 - "pci" PCIe core reset
274 - power-domains:
276 Value type: <prop-encoded-array>
281 - vdda-supply:
286 - vdda_phy-supply:
291 - vdda_refclk-supply:
296 - vddpe-3v3-supply:
301 - phys:
304 Definition: List of phandle(s) as listed in phy-names property
306 - phy-names:
311 - <name>-gpios:
313 Value type: <prop-encoded-array>
315 - "perst-gpios" PCIe endpoint reset signal line
316 - "wake-gpios" PCIe endpoint wake signal line
320 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
325 reg-names = "dbi", "elbi", "parf", "config";
327 linux,pci-domain = <0>;
328 bus-range = <0x00 0xff>;
329 num-lanes = <1>;
330 #address-cells = <3>;
331 #size-cells = <2>;
335 interrupt-names = "msi";
336 #interrupt-cells = <1>;
337 interrupt-map-mask = <0 0 0 0x7>;
338 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
347 clock-names = "core", "iface", "phy", "aux", "ref";
354 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
355 pinctrl-0 = <&pcie_pins_default>;
356 pinctrl-names = "default";
361 compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
366 reg-names = "parf", "dbi", "elbi", "config";
368 linux,pci-domain = <0>;
369 bus-range = <0x00 0xff>;
370 num-lanes = <1>;
371 #address-cells = <3>;
372 #size-cells = <2>;
376 interrupt-names = "msi";
377 #interrupt-cells = <1>;
378 interrupt-map-mask = <0 0 0 0x7>;
379 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
387 clock-names = "iface", "master_bus", "slave_bus", "aux";
389 reset-names = "core";
390 power-domains = <&gcc PCIE0_GDSC>;
391 vdda-supply = <&pma8084_l3>;
393 phy-names = "pciephy";
394 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
395 pinctrl-0 = <&pcie0_pins_default>;
396 pinctrl-names = "default";