Lines Matching +full:aux +full:- +full:output +full:- +full:power
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - enum:
16 - qcom,sdx55-pcie-ep
17 - qcom,sm8450-pcie-ep
18 - items:
19 - const: qcom,sdx65-pcie-ep
20 - const: qcom,sdx55-pcie-ep
24 - description: Qualcomm-specific PARF configuration registers
25 - description: DesignWare PCIe registers
26 - description: External local bus interface registers
27 - description: Address Translation Unit (ATU) registers
28 - description: Memory region used to map remote RC address space
29 - description: BAR memory region
31 reg-names:
33 - const: parf
34 - const: dbi
35 - const: elbi
36 - const: atu
37 - const: addr_space
38 - const: mmio
44 clock-names:
48 qcom,perst-regs:
52 $ref: /schemas/types.yaml#/definitions/phandle-array
54 - items:
55 - description: Syscon to TCSR system registers
56 - description: Perst enable offset
57 - description: Perst separation enable offset
61 - description: PCIe Global interrupt
62 - description: PCIe Doorbell interrupt
64 interrupt-names:
66 - const: global
67 - const: doorbell
69 reset-gpios:
73 wake-gpios:
74 description: GPIO used as WAKE# output signal
80 interconnect-names:
82 - const: pcie-mem
83 - const: cpu-pcie
88 reset-names:
91 power-domains:
97 phy-names:
100 num-lanes:
104 - compatible
105 - reg
106 - reg-names
107 - clocks
108 - clock-names
109 - interrupts
110 - interrupt-names
111 - reset-gpios
112 - interconnects
113 - interconnect-names
114 - resets
115 - reset-names
116 - power-domains
119 - $ref: pci-ep.yaml#
120 - if:
125 - qcom,sdx55-pcie-ep
130 - description: PCIe Auxiliary clock
131 - description: PCIe CFG AHB clock
132 - description: PCIe Master AXI clock
133 - description: PCIe Slave AXI clock
134 - description: PCIe Slave Q2A AXI clock
135 - description: PCIe Sleep clock
136 - description: PCIe Reference clock
137 clock-names:
139 - const: aux
140 - const: cfg
141 - const: bus_master
142 - const: bus_slave
143 - const: slave_q2a
144 - const: sleep
145 - const: ref
147 - if:
152 - qcom,sm8450-pcie-ep
157 - description: PCIe Auxiliary clock
158 - description: PCIe CFG AHB clock
159 - description: PCIe Master AXI clock
160 - description: PCIe Slave AXI clock
161 - description: PCIe Slave Q2A AXI clock
162 - description: PCIe Reference clock
163 - description: PCIe DDRSS SF TBU clock
164 - description: PCIe AGGRE NOC AXI clock
165 clock-names:
167 - const: aux
168 - const: cfg
169 - const: bus_master
170 - const: bus_slave
171 - const: slave_q2a
172 - const: ref
173 - const: ddrss_sf_tbu
174 - const: aggre_noc_axi
179 - |
180 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
181 #include <dt-bindings/gpio/gpio.h>
182 #include <dt-bindings/interconnect/qcom,sdx55.h>
183 #include <dt-bindings/interrupt-controller/arm-gic.h>
185 pcie_ep: pcie-ep@1c00000 {
186 compatible = "qcom,sdx55-pcie-ep";
193 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
203 clock-names = "aux", "cfg", "bus_master", "bus_slave",
206 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
210 interrupt-names = "global", "doorbell";
213 interconnect-names = "pcie-mem", "cpu-pcie";
214 reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
215 wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
217 reset-names = "core";
218 power-domains = <&gcc PCIE_GDSC>;
220 phy-names = "pciephy";
221 max-link-speed = <3>;
222 num-lanes = <2>;