Lines Matching +full:p2u +full:- +full:3
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and
5 snps,dw-pcie-ep.yaml.
10 - power-domains: A phandle to the node that controls power to the respective
20 "include/dt-bindings/power/tegra194-powergate.h" file.
21 - reg: A list of physical base address and length pairs for each set of
22 controller registers. Must contain an entry for each entry in the reg-names
24 - reg-names: Must include the following entries:
26 "config": As per the definition in snps,dw-pcie.yaml
32 - interrupts: A list of interrupt outputs of the controller. Must contain an
33 entry for each entry in the interrupt-names property.
34 - interrupt-names: Must include the following entries:
36 - clocks: Must contain an entry for each entry in clock-names.
37 See ../clocks/clock-bindings.txt for details.
38 - clock-names: Must include the following entries:
39 - core
40 - resets: Must contain an entry for each entry in reset-names.
42 - reset-names: Must include the following entries:
43 - apb
44 - core
45 - phys: Must contain a phandle to P2U PHY for each entry in phy-names.
46 - phy-names: Must include an entry for each active lane.
47 "p2u-N": where N ranges from 0 to one less than the total number of lanes
48 - nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
49 by controller-id. Following are the controller ids for each controller.
53 3: C3
56 - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
59 - compatible: Tegra19x must contain "nvidia,tegra194-pcie"
60 - device_type: Must be "pci" for RC mode
61 - interrupt-names: Must include the following entries:
63 - bus-range: Range of bus numbers associated with this controller
64 - #address-cells: Address representation for root ports (must be 3)
65 - cell 0 specifies the bus and device numbers of the root port:
68 - cell 1 denotes the upper 32 address bits and should be 0
69 - cell 2 contains the lower 32 address bits and is used to translate to the
71 - #size-cells: Size representation for root ports (must be 2)
72 - ranges: Describes the translation of addresses for root ports and standard
74 correspond to the address as described for the #address-cells property
77 #size-cells property above.
78 - Entries setup the mapping for the standard I/O, memory and
81 - 0x81000000: I/O memory region
82 - 0x82000000: non-prefetchable memory region
83 - 0xc2000000: prefetchable memory region
86 - #interrupt-cells: Size representation for interrupts (must be 1)
87 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
93 - compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
94 - reg-names: Must include the following entries:
96 - reset-gpios: Must contain a phandle to a GPIO controller followed by
101 - pinctrl-names: A list of pinctrl state names.
103 - "default": Configures PCIe I/O for proper operation.
104 - pinctrl-0: phandle for the 'default' state of pin configuration.
106 - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
107 - nvidia,update-fc-fixup: This is a boolean property and needs to be present to
114 a) speed is Gen-2 and MPS is 256B
115 b) speed is >= Gen-3 with any MPS
116 - nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
118 - nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
120 - nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
124 - vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
125 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
126 in p2972-0000 platform).
127 - vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
128 if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
129 in p2972-0000 platform).
132 - nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
135 NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
142 -----------------
145 compatible = "nvidia,tegra194-pcie";
146 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
150 reg-names = "appl", "config", "atu_dma";
152 #address-cells = <3>;
153 #size-cells = <2>;
155 num-lanes = <8>;
156 linux,pci-domain = <0>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
162 clock-names = "core";
166 reset-names = "apb", "core";
170 interrupt-names = "intr", "msi";
172 #interrupt-cells = <1>;
173 interrupt-map-mask = <0 0 0 0>;
174 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
178 supports-clkreq;
179 nvidia,aspm-cmrt-us = <60>;
180 nvidia,aspm-pwr-on-t-us = <20>;
181 nvidia,aspm-l0s-entrance-latency-us = <3>;
183 bus-range = <0x0 0xff>;
185 … 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
188 vddio-pex-ctl-supply = <&vdd_1v8ao>;
189 vpcie3v3-supply = <&vdd_3v3_pcie>;
190 vpcie12v-supply = <&vdd_12v_pcie>;
194 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
198 -----------------
200 pcie-ep@141a0000 {
201 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
202 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
207 reg-names = "appl", "atu_dma", "dbi", "addr_space";
209 num-lanes = <8>;
210 num-ib-windows = <2>;
211 num-ob-windows = <8>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
217 clock-names = "core";
221 reset-names = "apb", "core";
224 interrupt-names = "intr";
228 nvidia,aspm-cmrt-us = <60>;
229 nvidia,aspm-pwr-on-t-us = <20>;
230 nvidia,aspm-l0s-entrance-latency-us = <3>;
232 vddio-pex-ctl-supply = <&vdd_1v8ao>;
234 reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
236 nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
243 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
244 "p2u-5", "p2u-6", "p2u-7";