Lines Matching +full:p2u +full:- +full:3
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
29 - nvidia,tegra194-pcie-ep
30 - nvidia,tegra234-pcie-ep
34 - description: controller's application logic registers
35 - description: iATU and DMA registers. This is where the iATU (internal
38 - description: aperture where the Root Port's own configuration
40 - description: aperture used to map the remote Root Complex address space
42 reg-names:
44 - const: appl
45 - const: atu_dma
46 - const: dbi
47 - const: addr_space
51 - description: controller interrupt
53 interrupt-names:
55 - const: intr
59 - description: module clock
61 clock-names:
63 - const: core
67 - description: APB bus interface reset
68 - description: module reset
70 reset-names:
72 - const: apb
73 - const: core
75 reset-gpios:
83 phy-names:
86 - const: p2u-0
87 - const: p2u-1
88 - const: p2u-2
89 - const: p2u-3
90 - const: p2u-4
91 - const: p2u-5
92 - const: p2u-6
93 - const: p2u-7
95 power-domains:
101 Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h"
102 Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h"
106 - description: memory read client
107 - description: memory write client
109 interconnect-names:
111 - const: dma-mem # read
112 - const: write
114 dma-coherent: true
117 $ref: /schemas/types.yaml#/definitions/phandle-array
127 3: C3
136 3 : C3
146 - items:
147 - description: phandle to BPMP controller node
148 - description: PCIe controller ID
151 nvidia,aspm-cmrt-us:
155 nvidia,aspm-pwr-on-t-us:
159 nvidia,aspm-l0s-entrance-latency-us:
162 vddio-pex-ctl-supply:
165 nvidia,refclk-select-gpios:
169 nvidia,enable-ext-refclk:
177 nvidia,enable-srns:
181 Spread-Spectrum Clocking). NOTE: This is applicable only for
187 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
192 - interrupts
193 - interrupt-names
194 - clocks
195 - clock-names
196 - resets
197 - reset-names
198 - power-domains
199 - reset-gpios
200 - vddio-pex-ctl-supply
201 - num-lanes
202 - phys
203 - phy-names
204 - nvidia,bpmp
207 - |
208 #include <dt-bindings/clock/tegra194-clock.h>
209 #include <dt-bindings/gpio/tegra194-gpio.h>
210 #include <dt-bindings/interrupt-controller/arm-gic.h>
211 #include <dt-bindings/power/tegra194-powergate.h>
212 #include <dt-bindings/reset/tegra194-reset.h>
215 #address-cells = <2>;
216 #size-cells = <2>;
219 pcie-ep@141a0000 {
220 compatible = "nvidia,tegra194-pcie-ep";
225 reg-names = "appl", "atu_dma", "dbi", "addr_space";
227 interrupt-names = "intr";
230 clock-names = "core";
234 reset-names = "apb", "core";
236 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
242 nvidia,aspm-cmrt-us = <60>;
243 nvidia,aspm-pwr-on-t-us = <20>;
244 nvidia,aspm-l0s-entrance-latency-us = <3>;
246 vddio-pex-ctl-supply = <&vdd_1v8ao>;
248 reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
250 nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
253 num-lanes = <8>;
259 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
260 "p2u-5", "p2u-6", "p2u-7";
264 - |
265 #include <dt-bindings/clock/tegra234-clock.h>
266 #include <dt-bindings/gpio/tegra234-gpio.h>
267 #include <dt-bindings/interrupt-controller/arm-gic.h>
268 #include <dt-bindings/power/tegra234-powergate.h>
269 #include <dt-bindings/reset/tegra234-reset.h>
272 #address-cells = <2>;
273 #size-cells = <2>;
276 pcie-ep@141a0000 {
277 compatible = "nvidia,tegra234-pcie-ep";
278 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
283 reg-names = "appl", "atu_dma", "dbi", "addr_space";
286 interrupt-names = "intr";
289 clock-names = "core";
293 reset-names = "apb", "core";
297 nvidia,enable-ext-refclk;
298 nvidia,aspm-cmrt-us = <60>;
299 nvidia,aspm-pwr-on-t-us = <20>;
300 nvidia,aspm-l0s-entrance-latency-us = <3>;
302 vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;
304 reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
306 nvidia,refclk-select-gpios = <&gpio_aon
310 num-lanes = <8>;
316 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
317 "p2u-5", "p2u-6", "p2u-7";