Lines Matching full:pcie

1 * Marvell EBU PCIe interfaces
6     marvell,armada-370-pcie
7     marvell,armada-xp-pcie
8     marvell,dove-pcie
9     marvell,kirkwood-pcie
15 - ranges: ranges describing the MMIO registers to control the PCIe
17   the memory and I/O regions of each PCIe interface.
28   registers of this PCIe interface, from the base of the internal
46    * s is the PCI slot that corresponds to this PCIe interface
58 PCIe interface, having the following mandatory properties:
63   this PCIe interface.
64 - clocks: the clock associated to this PCIe interface
65 - marvell,pcie-port: the physical PCIe port number
74   define the mapping of the PCIe interface to interrupt numbers.
77 - marvell,pcie-lane: the physical PCIe lane number, for ports having
80 - num-lanes: number of SerDes PCIe lanes for this link (1 or 4)
83   specified will default to 100ms, as required by the PCIe specification.
92 pcie-controller {
93 	compatible = "marvell,armada-xp-pcie";
137 	pcie@1,0 {
148 		marvell,pcie-port = <0>;
149 		marvell,pcie-lane = <0>;
158 	pcie@2,0 {
169 		marvell,pcie-port = <0>;
170 		marvell,pcie-lane = <1>;
175 	pcie@3,0 {
186 		marvell,pcie-port = <0>;
187 		marvell,pcie-lane = <2>;
192 	pcie@4,0 {
203 		marvell,pcie-port = <0>;
204 		marvell,pcie-lane = <3>;
209 	pcie@5,0 {
220 		marvell,pcie-port = <1>;
221 		marvell,pcie-lane = <0>;
226 	pcie@6,0 {
237 		marvell,pcie-port = <1>;
238 		marvell,pcie-lane = <1>;
243 	pcie@7,0 {
254 		marvell,pcie-port = <1>;
255 		marvell,pcie-lane = <2>;
260 	pcie@8,0 {
271 		marvell,pcie-port = <1>;
272 		marvell,pcie-lane = <3>;
277 	pcie@9,0 {
288 		marvell,pcie-port = <2>;
289 		marvell,pcie-lane = <0>;
294 	pcie@a,0 {
305 		marvell,pcie-port = <3>;
306 		marvell,pcie-lane = <0>;