Lines Matching full:pcie
1 MediaTek Gen2 PCIe controller
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
22 - free_ck :for reference clock of PCIe subsys
34 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
48 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
53 entry for each PCIe port
59 PCIe port interface, having the following mandatory properties:
71 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
85 pcie: pcie@1a140000 {
86 compatible = "mediatek,mt7623-pcie";
88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
108 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
111 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
117 pcie@0,0 {
127 pcie@1,0 {
137 pcie@2,0 {
150 pcie1: pcie@112ff000 {
151 compatible = "mediatek,mt2712-pcie";
164 phy-names = "pcie-phy1";
182 pcie0: pcie@11700000 {
183 compatible = "mediatek,mt2712-pcie";
196 phy-names = "pcie-phy0";
216 pcie0: pcie@1a143000 {
217 compatible = "mediatek,mt7622-pcie";
253 pcie1: pcie@1a145000 {
254 compatible = "mediatek,mt7622-pcie";