Lines Matching +full:ports +full:- +full:lane +full:- +full:control
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
17 - $ref: /schemas/pci/pci-bus.yaml#
21 const: mediatek,mt7621-pci
25 - description: host-pci bridge registers
26 - description: pcie port 0 RC control registers
27 - description: pcie port 1 RC control registers
28 - description: pcie port 2 RC control registers
34 '^pcie@[0-2],0$':
36 $ref: /schemas/pci/pci-bus.yaml#
48 phy-names:
49 pattern: '^pcie-phy[0-2]$'
52 - "#interrupt-cells"
53 - interrupt-map-mask
54 - interrupt-map
55 - resets
56 - clocks
57 - phys
58 - phy-names
59 - ranges
64 - compatible
65 - reg
66 - ranges
67 - "#interrupt-cells"
68 - interrupt-map-mask
69 - interrupt-map
70 - reset-gpios
75 - |
76 #include <dt-bindings/gpio/gpio.h>
77 #include <dt-bindings/interrupt-controller/mips-gic.h>
80 compatible = "mediatek,mt7621-pci";
86 #address-cells = <3>;
87 #size-cells = <2>;
88 pinctrl-names = "default";
89 pinctrl-0 = <&pcie_pins>;
93 #interrupt-cells = <1>;
94 interrupt-map-mask = <0xF800 0 0 0>;
95 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
98 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
102 #address-cells = <3>;
103 #size-cells = <2>;
105 #interrupt-cells = <1>;
106 interrupt-map-mask = <0 0 0 0>;
107 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
111 phy-names = "pcie-phy0";
117 #address-cells = <3>;
118 #size-cells = <2>;
120 #interrupt-cells = <1>;
121 interrupt-map-mask = <0 0 0 0>;
122 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
126 phy-names = "pcie-phy1";
132 #address-cells = <3>;
133 #size-cells = <2>;
135 #interrupt-cells = <1>;
136 interrupt-map-mask = <0 0 0 0>;
137 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
141 phy-names = "pcie-phy2";