Lines Matching +full:pcie +full:- +full:scfg

1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 which is used to describe the PLL settings at the time of chip-reset.
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
15 - compatible: should contain the platform identifier such as:
17         "fsl,ls1021a-pcie"
18         "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19         "fsl,ls2088a-pcie"
20         "fsl,ls1088a-pcie"
21         "fsl,ls1046a-pcie"
22         "fsl,ls1043a-pcie"
23         "fsl,ls1012a-pcie"
24         "fsl,ls1028a-pcie"
26 	"fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"
27 	"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
28 	"fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
29 	"fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
30 	"fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"
31 - reg: base addresses and lengths of the PCIe controller register blocks.
32 - interrupts: A list of interrupt outputs of the controller. Must contain an
33   entry for each entry in the interrupt-names property.
34 - interrupt-names: It could include the following entries:
36 	 non MSI/MSI-X/INTx mode is used
38 	 non MSI/MSI-X/INTx mode is used
42 - fsl,pcie-scfg: Must include two entries.
43   The first entry must be a link to the SCFG device node
44   The second entry is the physical PCIe controller index starting from '0'.
45   This is used to get SCFG PEXN registers
46 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
51 - big-endian: If the PEX_LUT and PF register block is in big-endian, specify
56         pcie@3400000 {
57                 compatible = "fsl,ls1088a-pcie";
60                 reg-names = "regs", "config";
62                 interrupt-names = "aer";
63                 #address-cells = <3>;
64                 #size-cells = <2>;
66                 dma-coherent;
67                 num-viewport = <256>;
68                 bus-range = <0x0 0xff>;
70 …           0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
71                 msi-parent = <&its>;
72                 #interrupt-cells = <1>;
73                 interrupt-map-mask = <0 0 0 7>;
74                 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
78                 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */