Lines Matching +full:0 +full:xf6000000
77 reg = <0x0 0xf4000000 0x0 0x1000>,
78 <0x0 0xff3fe000 0x0 0x1000>,
79 <0x0 0xf3f20000 0x0 0x40000>,
80 <0x0 0xf5000000 0x0 0x2000>;
82 bus-range = <0x0 0xff>;
86 ranges = <0x02000000 0x0 0x00000000
87 0x0 0xf6000000
88 0x0 0x02000000>;
91 interrupts = <0 283 4>;
93 interrupt-map-mask = <0xf800 0 0 7>;
94 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
95 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
96 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
97 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
109 reg = <0x0 0xf4000000 0x0 0x1000000>,
110 <0x0 0xfc180000 0x0 0x1000>,
111 <0x0 0xf5000000 0x0 0x2000>;
113 bus-range = <0x0 0xff>;
118 ranges = <0x02000000 0x0 0x00000000
119 0x0 0xf6000000
120 0x0 0x02000000>;
125 interrupt-map-mask = <0 0 0 7>;
126 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
127 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
128 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
129 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
130 reset-gpios = <&gpio7 0 0>;
131 hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>;
132 pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
133 reg = <0 0 0 0 0>;
140 pcie@0,0 { // Lane 0: upstream
141 reg = <0 0 0 0 0>;
148 pcie@1,0 { // Lane 4: M.2
149 reg = <0x0800 0 0 0 0>;
152 reset-gpios = <&gpio3 1 0>;
158 pcie@5,0 { // Lane 5: Mini PCIe
159 reg = <0x2800 0 0 0 0>;
162 reset-gpios = <&gpio27 4 0 >;
168 pcie@7,0 { // Lane 6: Ethernet
169 reg = <0x03800 0 0 0 0>;
172 reset-gpios = <&gpio25 2 0 >;