Lines Matching +full:imx6q +full:- +full:gpc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
25 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie
30 - fsl,imx8mm-pcie
31 - fsl,imx8mp-pcie
35 - description: Data Bus Interface (DBI) registers.
36 - description: PCIe configuration space region.
38 reg-names:
40 - const: dbi
41 - const: config
46 - description: PCIe bridge clock.
47 - description: PCIe bus clock.
48 - description: PCIe PHY clock.
49 - description: Additional required clock entry for imx6sx-pcie,
50 imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
52 clock-names:
58 - description: builtin MSI controller.
60 interrupt-names:
62 - const: msi
64 reset-gpio:
66 reset signal. It's not polarity aware and defaults to active-low reset
69 reset-gpio-active-high:
71 specified in the "reset-gpio" property is reversed (H=reset state,
76 - compatible
77 - reg
78 - reg-names
79 - "#address-cells"
80 - "#size-cells"
81 - device_type
82 - bus-range
83 - ranges
84 - interrupts
85 - interrupt-names
86 - "#interrupt-cells"
87 - interrupt-map-mask
88 - interrupt-map
91 - $ref: /schemas/pci/snps,dw-pcie.yaml#
92 - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
93 - if:
97 - fsl,imx6sx-pcie
102 clock-names:
104 - const: pcie
105 - const: pcie_bus
106 - const: pcie_phy
107 - const: pcie_inbound_axi
109 - if:
113 - fsl,imx8mq-pcie
118 clock-names:
120 - const: pcie
121 - const: pcie_bus
122 - const: pcie_phy
123 - const: pcie_aux
125 - if:
129 - fsl,imx6q-pcie
130 - fsl,imx6qp-pcie
131 - fsl,imx7d-pcie
136 clock-names:
138 - const: pcie
139 - const: pcie_bus
140 - const: pcie_phy
142 - if:
146 - fsl,imx8mm-pcie
147 - fsl,imx8mp-pcie
152 clock-names:
154 - const: pcie
155 - const: pcie_bus
156 - const: pcie_aux
161 - |
162 #include <dt-bindings/clock/imx6qdl-clock.h>
163 #include <dt-bindings/interrupt-controller/arm-gic.h>
166 compatible = "fsl,imx6q-pcie";
169 reg-names = "dbi", "config";
170 #address-cells = <3>;
171 #size-cells = <2>;
173 bus-range = <0x00 0xff>;
176 num-lanes = <1>;
178 interrupt-names = "msi";
179 #interrupt-cells = <1>;
180 interrupt-map-mask = <0 0 0 0x7>;
181 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
182 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
183 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
184 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
188 clock-names = "pcie", "pcie_bus", "pcie_phy";