Lines Matching +full:imx8mq +full:- +full:clock
4 and thus inherits all the common properties defined in designware-pcie.txt.
7 - compatible:
8 - "fsl,imx6q-pcie"
9 - "fsl,imx6sx-pcie",
10 - "fsl,imx6qp-pcie"
11 - "fsl,imx7d-pcie"
12 - "fsl,imx8mq-pcie"
13 - reg: base address and length of the PCIe controller
14 - interrupts: A list of interrupt outputs of the controller. Must contain an
15 entry for each entry in the interrupt-names property.
16 - interrupt-names: Must include the following entries:
17 - "msi": The interrupt that is asserted when an MSI is received
18 - clock-names: Must include the following additional entries:
19 - "pcie_phy"
22 - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
23 - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
24 - fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20
25 - fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127
26 - fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127
27 - fsl,max-link-speed: Specify PCI gen for link capability. Must be '2' for
28 gen2, otherwise will default to gen1. Note that the IMX6 LVDS clock outputs
30 compliant clock generator should be used and configured.
31 - reset-gpio: Should specify the GPIO for controlling the PCI bus device reset
32 signal. It's not polarity aware and defaults to active-low reset sequence
34 - reset-gpio-active-high: If present then the reset sequence using the GPIO
35 specified in the "reset-gpio" property is reversed (H=reset state,
37 - vpcie-supply: Should specify the regulator in charge of PCIe port power.
41 - vph-supply: Should specify the regulator in charge of VPH one of the three
45 Additional required properties for imx6sx-pcie:
46 - clock names: Must include the following additional entries:
47 - "pcie_inbound_axi"
48 - power-domains: Must be set to phandles pointing to the DISPLAY and
50 - power-domain-names: Must be "pcie", "pcie_phy"
52 Additional required properties for imx7d-pcie and imx8mq-pcie:
53 - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
54 - resets: Must contain phandles to PCIe-related reset lines exposed by SRC
56 - reset-names: Must contain the following entries:
57 - "pciephy"
58 - "apps"
59 - "turnoff"
60 - fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node.
62 Additional required properties for imx8mq-pcie:
63 - clock-names: Must include the following additional entries:
64 - "pcie_aux"
69 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
72 reg-names = "dbi", "config";
73 #address-cells = <3>;
74 #size-cells = <2>;
79 num-lanes = <1>;
81 interrupt-names = "msi";
82 #interrupt-cells = <1>;
83 interrupt-map-mask = <0 0 0 0x7>;
84 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
89 clock-names = "pcie", "pcie_bus", "pcie_phy";
95 PCI-e controller via the fsl,imx7d-pcie-phy phandle.
98 - compatible:
99 - "fsl,imx7d-pcie-phy"
100 - reg: base address and length of the PCIe PHY controller