Lines Matching +full:phy +full:- +full:ref +full:- +full:clk

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Lucas Stach <l.stach@pengutronix.de>
11   - Richard Zhu <hongxing.zhu@nxp.com>
15   thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
22       - fsl,imx8mm-pcie-ep
23       - fsl,imx8mq-pcie-ep
24       - fsl,imx8mp-pcie-ep
29   reg-names:
31       - const: dbi
32       - const: addr_space
37       - description: PCIe bridge clock.
38       - description: PCIe bus clock.
39       - description: PCIe PHY clock.
40       - description: Additional required clock entry for imx6sx-pcie,
41            imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
43   clock-names:
49       - description: builtin eDMA interrupter.
51   interrupt-names:
53       - const: dma
56   - compatible
57   - reg
58   - reg-names
59   - interrupts
60   - interrupt-names
63   - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
64   - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
65   - if:
69             - fsl,imx8mq-pcie-ep
74         clock-names:
76             - const: pcie
77             - const: pcie_bus
78             - const: pcie_phy
79             - const: pcie_aux
84         clock-names:
86             - const: pcie
87             - const: pcie_bus
88             - const: pcie_aux
94   - |
95     #include <dt-bindings/clock/imx8mp-clock.h>
96     #include <dt-bindings/power/imx8mp-power.h>
97     #include <dt-bindings/reset/imx8mp-reset.h>
98     #include <dt-bindings/interrupt-controller/arm-gic.h>
100     pcie_ep: pcie-ep@33800000 {
101       compatible = "fsl,imx8mp-pcie-ep";
103       reg-names = "dbi", "addr_space";
104       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
105                <&clk IMX8MP_CLK_HSIO_AXI>,
106                <&clk IMX8MP_CLK_PCIE_ROOT>;
107       clock-names = "pcie", "pcie_bus", "pcie_aux";
108       assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
109       assigned-clock-rates = <10000000>;
110       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
111       num-lanes = <1>;
113       interrupt-names = "dma";
114       fsl,max-link-speed = <3>;
115       power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
118       reset-names = "apps", "turnoff";
120       phy-names = "pcie-phy";
121       num-ib-windows = <4>;
122       num-ob-windows = <4>;