Lines Matching +full:pcie +full:- +full:ob

1 * Synopsys DesignWare PCIe interface
4 - compatible:
5 	"snps,dw-pcie" for RC mode;
6 	"snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - device_type: set to "pci"
18 - ranges: ranges for the PCI memory and I/O regions
19 - #interrupt-cells: set to <1>
20 - interrupt-map-mask and interrupt-map: standard PCI
21 	properties to define the mapping of the PCIe interface to interrupt
24 - num-ib-windows: number of inbound address translation windows
25 - num-ob-windows: number of outbound address translation windows
28 - num-lanes: number of lanes to use (this property should be specified unless
30 - reset-gpio: GPIO pin number of power good signal
31 - clocks: Must contain an entry for each entry in clock-names.
32 	See ../clocks/clock-bindings.txt for details.
33 - clock-names: Must include the following entries:
34 	- "pcie"
35 	- "pcie_bus"
36 - snps,enable-cdm-check: This is a boolean property and if present enables
38    for data corruption. CDM registers include standard PCIe configuration
42 - num-viewport: number of view ports configured in hardware. If a platform
44 - bus-range: PCI bus numbers covered (it is recommended for new devicetrees
46   0x00-0xff is assumed if not present)
49 - max-functions: maximum number of functions that can be configured
53 	pcie: pcie@dfc00000 {
54 		compatible = "snps,dw-pcie";
57 		reg-names = "dbi", "config";
58 		#address-cells = <3>;
59 		#size-cells = <2>;
64 		#interrupt-cells = <1>;
65 		num-lanes = <1>;
68 	pcie: pcie@dfc00000 {
69 		compatible = "snps,dw-pcie-ep";
73 		reg-names = "dbi", "dbi2", "addr_space";
74 		num-ib-windows = <6>;
75 		num-ob-windows = <2>;
76 		num-lanes = <1>;