Lines Matching +full:pcie +full:- +full:msi +full:- +full:inten
1 * Broadcom iProc PCIe controller with the platform bus interface
4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
18 mapping of the PCIe interface to interrupt numbers
19 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
20 - bus-range: PCI bus numbers covered
21 - #address-cells: set to <3>
22 - #size-cells: set to <2>
23 - device_type: set to "pci"
24 - ranges: ranges for the PCI memory and I/O regions
27 - phys: phandle of the PCIe PHY device
28 - phy-names: must be "pcie-phy"
29 - dma-coherent: present if DMA operations are coherent
30 - dma-ranges: Some PAXB-based root complexes do not have inbound mapping done
34 - brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done
37 If the brcm,pcie-ob property is present, the following properties become
41 - brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal
42 address used by the iProc PCIe core (not the PCIe address)
44 MSI support (optional):
46 For older platforms without MSI integrated in the GIC, iProc PCIe core provides
47 an event queue based MSI support. The iProc MSI uses host memories to store
48 MSI posted writes in the event queues
50 On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used
52 - msi-map: Maps a Requester ID to an MSI controller and associated MSI
55 - msi-parent: Link to the device node of the MSI controller, used when no MSI
56 sideband data is passed between the iProc PCIe controller and the MSI
60 the use of 'msi-map' and 'msi-parent':
61 Documentation/devicetree/bindings/pci/pci-msi.txt
62 Documentation/devicetree/bindings/interrupt-controller/msi.txt
64 When the iProc event queue based MSI is used, one needs to define the
65 following properties in the MSI device node:
66 - compatible: Must be "brcm,iproc-msi"
67 - msi-controller: claims itself as an MSI controller
68 - interrupts: List of interrupt IDs from its parent interrupt device
71 - brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
72 require the interrupt enable registers to be set explicitly to enable MSI
75 pcie0: pcie@18012000 {
76 compatible = "brcm,iproc-pcie";
79 #interrupt-cells = <1>;
80 interrupt-map-mask = <0 0 0 0>;
81 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
83 linux,pci-domain = <0>;
85 bus-range = <0x00 0xff>;
87 #address-cells = <3>;
88 #size-cells = <2>;
94 phy-names = "pcie-phy";
96 brcm,pcie-ob;
97 brcm,pcie-ob-axi-offset = <0x00000000>;
99 msi-parent = <&msi0>;
101 /* iProc event queue based MSI */
102 msi0: msi@18012000 {
103 compatible = "brcm,iproc-msi";
104 msi-controller;
105 interrupt-parent = <&gic>;
113 pcie1: pcie@18013000 {
114 compatible = "brcm,iproc-pcie";
117 #interrupt-cells = <1>;
118 interrupt-map-mask = <0 0 0 0>;
119 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
121 linux,pci-domain = <1>;
123 bus-range = <0x00 0xff>;
125 #address-cells = <3>;
126 #size-cells = <2>;
132 phy-names = "pcie-phy";