Lines Matching +full:axi +full:- +full:dma +full:- +full:1
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
16 Management configuration is done through the AXI interface, while payload is
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
34 and length of the AXI DMA controller IO space, unless
35 axistream-connected is specified, in which case the reg
41 - description: Ethernet core interrupt
42 - description: Tx DMA interrupt
43 - description: Rx DMA interrupt
45 Ethernet core interrupt is optional. If axistream-connected property is
46 present DMA node should contains TX/RX DMA interrupts else DMA interrupt
48 minItems: 1
50 phy-handle: true
57 phy-mode:
59 - mii
60 - gmii
61 - rgmii
62 - sgmii
63 - 1000BaseX
65 xlnx,phy-type:
67 Do not use, but still accepted in preference to phy-mode.
74 1 to enable partial TX checksum offload and 2 to enable full TX
77 enum: [0, 1, 2]
82 1 to enable partial RX checksum offload and 2 to enable full RX
85 enum: [0, 1, 2]
87 xlnx,switch-x-sgmii:
91 SGMII modes. If set, the phy-mode should be set to match the mode
96 - description: Clock for AXI register slave interface.
97 - description: AXI4-Stream clock for TXD RXD TXC and RXS interfaces.
98 - description: Ethernet reference clock, used by signal delay primitives
100 - description: MGT reference clock (used by optional internal PCS/PMA PHY)
102 clock-names:
104 - const: s_axi_lite_clk
105 - const: axis_clk
106 - const: ref_clk
107 - const: mgt_clk
109 axistream-connected:
111 description: Phandle of AXI DMA controller which contains the resources
112 used by this device. If this is specified, the DMA-related resources
113 from that device (DMA registers and DMA TX/RX interrupts) rather than
119 pcs-handle:
120 description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
121 modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
122 and "phy-handle" should point to an external PHY if exists.
123 maxItems: 1
128 description: TX and RX DMA channel phandle
130 dma-names:
132 pattern: "^[tr]x_chan([0-9]|1[0-5])$"
134 Should be "tx_chan0", "tx_chan1" ... "tx_chan15" for DMA Tx channel
135 Should be "rx_chan0", "rx_chan1" ... "rx_chan15" for DMA Rx channel
140 - compatible
141 - interrupts
142 - reg
143 - xlnx,rxmem
144 - phy-handle
147 - $ref: /schemas/net/ethernet-controller.yaml#
152 - |
154 compatible = "xlnx,axi-ethernet-1.00.a";
155 interrupts = <2 0 1>;
156 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
158 phy-mode = "mii";
160 dmas = <&xilinx_dma 0>, <&xilinx_dma 1>;
161 dma-names = "tx_chan0", "rx_chan0";
165 phy-handle = <&phy0>;
168 #address-cells = <1>;
169 #size-cells = <0>;
170 phy0: ethernet-phy@1 {
171 device_type = "ethernet-phy";
172 reg = <1>;
177 - |
179 compatible = "xlnx,axi-ethernet-1.00.a";
181 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
183 phy-mode = "mii";
188 phy-handle = <&phy1>;
189 axistream-connected = <&dma>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 phy1: ethernet-phy@1 {
195 device_type = "ethernet-phy";
196 reg = <1>;