Lines Matching +full:two +full:- +full:ethernet
1 XILINX AXI ETHERNET Device Tree Bindings
2 --------------------------------------------------------
4 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
5 provides connectivity to an external ethernet PHY supporting different
6 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
27 instead, and only the Ethernet core interrupt is optionally
29 - phy-handle : Should point to the external phy device if exists. Pointing
31 See ethernet.txt file in the same directory.
32 - xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware
35 - phy-mode : See ethernet.txt
36 - xlnx,phy-type : Deprecated, do not use, but still accepted in preference
37 to phy-mode.
38 - xlnx,txcsum : 0 or empty for disabling TX checksum offload,
41 - xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload
42 - xlnx,switch-x-sgmii : Boolean to indicate the Ethernet core is configured to
43 support both 1000BaseX and SGMII modes. If set, the phy-mode
46 - clock-names: Tuple listing input clock names. Possible clocks:
48 axis_clk: AXI4-Stream clock for TXD RXD TXC and RXS interfaces
49 ref_clk: Ethernet reference clock, used by signal delay
56 specified, the clock rate is auto-detected from the CPU clock
58 trees should specify all applicable clocks by name - the
61 - clocks: Phandles to input clocks matching clock-names. Refer to common
63 - axistream-connected: Reference to another node which contains the resources
65 If this is specified, the DMA-related resources from that
68 - mdio : Child node for MDIO bus. Must be defined if PHY access is
71 Non-standard MDIO bus frequency is supported via
72 "clock-frequency", see mdio.yaml.
74 - pcs-handle: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
75 modes, where "pcs-handle" should be used to point
76 to the PCS/PMA PHY, and "phy-handle" should point to an
80 axi_ethernet_eth: ethernet@40c00000 {
81 compatible = "xlnx,axi-ethernet-1.00.a";
83 interrupt-parent = <µblaze_0_axi_intc>;
85 clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
87 phy-mode = "mii";
92 phy-handle = <&phy0>;
94 #address-cells = <1>;
95 #size-cells = <0>;
97 device_type = "ethernet-phy";