Lines Matching +full:dra7 +full:- +full:cpsw +full:- +full:switch
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI SoC Ethernet Switch Controller (CPSW)
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
15 communication and can be configured as an ethernet switch. It provides the
24 - const: ti,cpsw-switch
25 - items:
26 - const: ti,am335x-cpsw-switch
27 - const: ti,cpsw-switch
28 - items:
29 - const: ti,am4372-cpsw-switch
30 - const: ti,cpsw-switch
31 - items:
32 - const: ti,dra7-cpsw-switch
33 - const: ti,cpsw-switch
38 The physical base address and size of full the CPSW module IO range
40 '#address-cells':
43 '#size-cells':
50 description: CPSW functional clock
52 clock-names:
54 - const: fck
58 - description: RX_THRESH interrupt
59 - description: RX interrupt
60 - description: TX interrupt
61 - description: MISC interrupt
63 interrupt-names:
65 - const: rx_thresh
66 - const: rx
67 - const: tx
68 - const: misc
70 pinctrl-names: true
78 ethernet-ports:
83 '#address-cells':
85 '#size-cells':
91 description: CPSW external ports
93 $ref: ethernet-controller.yaml#
99 - enum: [1, 2]
100 description: CPSW port number
104 description: phandle on phy-gmii-sel PHY
109 ti,dual-emac-pvid:
115 ports. Default value - CPSW port number.
118 - reg
119 - phys
132 clock-names:
134 - const: cpts
149 - clocks
150 - clock-names
156 CPSW MDIO bus.
157 $ref: ti,davinci-mdio.yaml#
161 - compatible
162 - reg
163 - ranges
164 - clocks
165 - clock-names
166 - interrupts
167 - interrupt-names
168 - '#address-cells'
169 - '#size-cells'
174 - |
175 #include <dt-bindings/interrupt-controller/irq.h>
176 #include <dt-bindings/interrupt-controller/arm-gic.h>
177 #include <dt-bindings/clock/dra7.h>
179 mac_sw: switch@0 {
180 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
184 clock-names = "fck";
185 #address-cells = <1>;
186 #size-cells = <1>;
193 interrupt-names = "rx_thresh", "rx", "tx", "misc";
195 ethernet-ports {
196 #address-cells = <1>;
197 #size-cells = <0>;
202 mac-address = [ 00 00 00 00 00 00 ];
204 phy-handle = <ðphy0_sw>;
205 phy-mode = "rgmii";
206 ti,dual-emac-pvid = <1>;
212 mac-address = [ 00 00 00 00 00 00 ];
214 phy-handle = <ðphy1_sw>;
215 phy-mode = "rgmii";
216 ti,dual-emac-pvid = <2>;
221 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
224 clock-names = "fck";
225 #address-cells = <1>;
226 #size-cells = <0>;
229 ethphy0_sw: ethernet-phy@0 {
233 ethphy1_sw: ethernet-phy@1 {
240 clock-names = "cpts";