Lines Matching +full:0 +full:xc00

37 		reg = <0xfeb20000 0x10000>,
38 		      <0xfeb36000 0x1000>;
41 		clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
51 		#size-cells = <0>;
52 		phy0: ethernet-phy@0 {
53 			reg = <0>;
57 		pinctrl-0 = <&mdio_pins_a>;
62 		reg = <0xfeb38000 0x1000>;
86 		reg = <0x0 0x38800000 0x0 0x10000>,
87 		      <0x0 0x38816000 0x0 0x1000>;
88 		interrupts = <0 256 4>;
90 		clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
100 		#size-cells = <0>;
108 		reg = <0x0 0x00410400 0x0 0xc00>, /* Base address */
109 		      <0x0 0x00410000 0x0 0x400>; /* Per-lane digital */
110 		interrupts = <0 254 1>;