Lines Matching +full:phy +full:- +full:ref +full:- +full:clk
1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR803x PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
23 $ref: /schemas/types.yaml#/definitions/uint32
26 qca,clk-out-strength:
28 $ref: /schemas/types.yaml#/definitions/uint32
31 qca,disable-smarteee:
35 qca,keep-pll-enabled:
43 qca,disable-hibernation-mode:
46 that the hardware of PHY will not enter power saving mode when the
51 qca,smarteee-tw-us-100m:
53 $ref: /schemas/types.yaml#/definitions/uint32
57 qca,smarteee-tw-us-1g:
59 $ref: /schemas/types.yaml#/definitions/uint32
63 vddio-supply:
67 The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
68 either connect this to the vddio-regulator (1.5V / 1.8V) or the
69 vddh-regulator (2.5V).
73 vddio-regulator:
77 $ref: /schemas/regulator/regulator.yaml
80 vddh-regulator:
83 Dummy subnode to model the external connection of the PHY VDDH
85 $ref: /schemas/regulator/regulator.yaml
91 - |
92 #include <dt-bindings/net/qca-ar803x.h>
95 #address-cells = <1>;
96 #size-cells = <0>;
98 phy-mode = "rgmii-id";
100 ethernet-phy@0 {
103 qca,clk-out-frequency = <125000000>;
104 qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
106 vddio-supply = <&vddio>;
108 vddio: vddio-regulator {
109 regulator-min-microvolt = <1800000>;
110 regulator-max-microvolt = <1800000>;
114 - |
115 #include <dt-bindings/net/qca-ar803x.h>
118 #address-cells = <1>;
119 #size-cells = <0>;
121 phy-mode = "rgmii-id";
123 ethernet-phy@0 {
126 qca,clk-out-frequency = <50000000>;
127 qca,keep-pll-enabled;
129 vddio-supply = <&vddh>;
131 vddh: vddh-regulator {