Lines Matching +full:eee +full:- +full:pcs
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
23 - const: mac
24 - const: xpcs
30 interrupt-names:
33 - const: common
34 - const: macsec-ns
35 - const: macsec
40 clock-names:
42 - const: mgbe
43 - const: mac
44 - const: mac-divider
45 - const: ptp-ref
46 - const: rx-input-m
47 - const: rx-input
48 - const: tx
49 - const: eee-pcs
50 - const: rx-pcs-input
51 - const: rx-pcs-m
52 - const: rx-pcs
53 - const: tx-pcs
58 reset-names:
60 - const: mac
61 - const: pcs
65 - description: memory read client
66 - description: memory write client
68 interconnect-names:
70 - const: dma-mem
71 - const: write
76 power-domains:
79 phy-handle: true
81 phy-mode:
84 - usxgmii
85 - 10gbase-kr
94 - compatible
95 - reg
96 - interrupts
97 - interrupt-names
98 - clocks
99 - clock-names
100 - resets
101 - reset-names
102 - power-domains
103 - phy-handle
104 - phy-mode
109 - |
110 #include <dt-bindings/clock/tegra234-clock.h>
111 #include <dt-bindings/interrupt-controller/arm-gic.h>
112 #include <dt-bindings/memory/tegra234-mc.h>
113 #include <dt-bindings/power/tegra234-powergate.h>
114 #include <dt-bindings/reset/tegra234-reset.h>
117 compatible = "nvidia,tegra234-mgbe";
121 reg-names = "hypervisor", "mac", "xpcs";
123 interrupt-names = "common";
136 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
137 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
138 "rx-pcs", "tx-pcs";
141 reset-names = "mac", "pcs";
144 interconnect-names = "dma-mem", "write";
146 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
148 phy-handle = <&mgbe0_phy>;
149 phy-mode = "usxgmii";
152 #address-cells = <1>;
153 #size-cells = <0>;
156 compatible = "ethernet-phy-ieee802.3-c45";
159 #phy-cells = <0>;