Lines Matching +full:syscon +full:- +full:rgmii +full:- +full:delay
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
33 - items:
34 - enum:
35 - mediatek,mt2712-gmac
36 - const: snps,dwmac-4.20a
37 - items:
38 - enum:
39 - mediatek,mt8195-gmac
40 - const: snps,dwmac-5.10a
41 - items:
42 - enum:
43 - mediatek,mt8188-gmac
44 - const: mediatek,mt8195-gmac
45 - const: snps,dwmac-5.10a
50 - description: AXI clock
51 - description: APB clock
52 - description: MAC Main clock
53 - description: PTP clock
54 - description: RMII reference clock provided by MAC
55 - description: MAC clock gate
57 clock-names:
60 - const: axi
61 - const: apb
62 - const: mac_main
63 - const: ptp_ref
64 - const: rmii_internal
65 - const: mac_cg
67 power-domains:
73 The phandle to the syscon node that control ethernet
74 interface and timing delay.
76 mediatek,tx-delay-ps:
78 The internal TX clock delay (provided by this driver) in nanoseconds.
79 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
83 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
86 mediatek,rx-delay-ps:
88 The internal RX clock delay (provided by this driver) in nanoseconds.
89 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
93 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
96 mediatek,rmii-rxc:
102 mediatek,rmii-clk-from-mac:
108 mediatek,txc-inverse:
112 1. tx clock will be inversed in MII/RGMII case,
118 mediatek,rxc-inverse:
122 1. rx clock will be inversed in MII/RGMII case.
128 mediatek,mac-wol:
131 If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled.
135 - compatible
136 - reg
137 - interrupts
138 - interrupt-names
139 - clocks
140 - clock-names
141 - phy-mode
142 - mediatek,pericfg
147 - |
148 #include <dt-bindings/clock/mt2712-clk.h>
149 #include <dt-bindings/gpio/gpio.h>
150 #include <dt-bindings/interrupt-controller/arm-gic.h>
151 #include <dt-bindings/interrupt-controller/irq.h>
152 #include <dt-bindings/power/mt2712-power.h>
155 compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
158 interrupt-names = "macirq";
159 phy-mode = "rgmii-rxid";
160 mac-address = [00 55 7b b5 7d f7];
161 clock-names = "axi",
171 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
174 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
177 power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
179 mediatek,tx-delay-ps = <1530>;
182 snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
183 snps,reset-delays-us = <0 10000 10000>;