Lines Matching +full:tx +full:- +full:delay +full:- +full:ps

9 - compatible:  Should be "mediatek,mt2712-gmac" for MT2712 SoC
10 - reg:  Address and length of the register set for the device
11 - interrupts:  Should contain the MAC interrupts
12 - interrupt-names: Should contain a list of interrupt names corresponding to
15 - clocks: Must contain a phandle for each entry in clock-names.
16 - clock-names: The name of the clock listed in the clocks property. These are
18 - mac-address: See ethernet.txt in the same directory
19 - phy-mode: See ethernet.txt in the same directory
20 - mediatek,pericfg: A phandle to the syscon node that control ethernet
21 	interface and timing delay.
24 - mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
27 - mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
30 Both delay properties need to be a multiple of 170 for RGMII interface,
32 Both delay properties need to be a multiple of 550 for MII/RMII interface,
35 - mediatek,rmii-rxc: boolean property, if present indicates that the RMII
39 - mediatek,rmii-clk-from-mac: boolean property, if present indicates that
41 - mediatek,txc-inverse: boolean property, if present indicates that
42 	1. tx clock will be inversed in MII/RGMII case,
43 	2. tx clock inside MAC will be inversed relative to reference clock
47 - mediatek,rxc-inverse: boolean property, if present indicates that
53 - assigned-clocks: mac_main and ptp_ref clocks
54 - assigned-clock-parents: parent clocks of the assigned clocks
58 		compatible = "mediatek,mt2712-gmac";
61 		interrupt-names = "macirq";
62 		phy-mode ="rgmii-rxid";
63 		mac-address = [00 55 7b b5 7d f7];
64 		clock-names = "axi",
74 		assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
77 		assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
80 		power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
82 		mediatek,tx-delay-ps = <1530>;
83 		mediatek,rx-delay-ps = <1530>;
84 		mediatek,rmii-rxc;
85 		mediatek,txc-inverse;
86 		mediatek,rxc-inverse;
89 		snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
90 		snps,reset-active-low;