Lines Matching +full:rx +full:- +full:clock +full:- +full:name

9 - compatible:  Should be "mediatek,mt2712-gmac" for MT2712 SoC
10 - reg:  Address and length of the register set for the device
11 - interrupts:  Should contain the MAC interrupts
12 - interrupt-names: Should contain a list of interrupt names corresponding to
15 - clocks: Must contain a phandle for each entry in clock-names.
16 - clock-names: The name of the clock listed in the clocks property. These are
18 - mac-address: See ethernet.txt in the same directory
19 - phy-mode: See ethernet.txt in the same directory
20 - mediatek,pericfg: A phandle to the syscon node that control ethernet
24 - mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
26 	It should be defined for RMII interface when the reference clock is from MT2712 SoC.
27 - mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
35 - mediatek,rmii-rxc: boolean property, if present indicates that the RMII
36 	reference clock, which is from external PHYs, is connected to RXC pin
39 - mediatek,rmii-clk-from-mac: boolean property, if present indicates that
40 	MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only.
41 - mediatek,txc-inverse: boolean property, if present indicates that
42 	1. tx clock will be inversed in MII/RGMII case,
43 	2. tx clock inside MAC will be inversed relative to reference clock
45 	3. the reference clock, which outputs to TXC pin will be inversed in RMII case
46 	   when the reference clock is from MT2712 SoC.
47 - mediatek,rxc-inverse: boolean property, if present indicates that
48 	1. rx clock will be inversed in MII/RGMII case.
49 	2. reference clock will be inversed when arrived at MAC in RMII case, when
50 	   the reference clock is from external PHYs.
51 	3. the inside clock, which be sent to MAC, will be inversed in RMII case when
52 	   the reference clock is from MT2712 SoC.
53 - assigned-clocks: mac_main and ptp_ref clocks
54 - assigned-clock-parents: parent clocks of the assigned clocks
58 		compatible = "mediatek,mt2712-gmac";
61 		interrupt-names = "macirq";
62 		phy-mode ="rgmii-rxid";
63 		mac-address = [00 55 7b b5 7d f7];
64 		clock-names = "axi",
74 		assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
77 		assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
80 		power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
82 		mediatek,tx-delay-ps = <1530>;
83 		mediatek,rx-delay-ps = <1530>;
84 		mediatek,rmii-rxc;
85 		mediatek,txc-inverse;
86 		mediatek,rxc-inverse;
89 		snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
90 		snps,reset-active-low;