Lines Matching +full:reg +full:- +full:init

8 - #address-cells = <1>;
9 - #size-cells = <0>;
12 - mdio-parent-bus : phandle to the parent MDIO bus.
14 - Other properties specific to the multiplexer/switch hardware.
17 - #address-cells = <1>;
18 - #size-cells = <0>;
19 - reg : The sub-bus number.
26 		compatible = "cavium,octeon-3860-mdio";
27 		#address-cells = <1>;
28 		#size-cells = <0>;
29 		reg = <0x11800 0x00001900 0x0 0x40>;
33 	   An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
37 	mdio-mux {
38 		compatible = "mdio-mux-gpio";
40 		mdio-parent-bus = <&smi1>;
41 		#address-cells = <1>;
42 		#size-cells = <0>;
45 			reg = <2>;
46 			#address-cells = <1>;
47 			#size-cells = <0>;
49 			phy11: ethernet-phy@1 {
50 				reg = <1>;
51 				marvell,reg-init = <3 0x10 0 0x5777>,
55 				interrupt-parent = <&gpio>;
58 			phy12: ethernet-phy@2 {
59 				reg = <2>;
60 				marvell,reg-init = <3 0x10 0 0x5777>,
64 				interrupt-parent = <&gpio>;
67 			phy13: ethernet-phy@3 {
68 				reg = <3>;
69 				marvell,reg-init = <3 0x10 0 0x5777>,
73 				interrupt-parent = <&gpio>;
76 			phy14: ethernet-phy@4 {
77 				reg = <4>;
78 				marvell,reg-init = <3 0x10 0 0x5777>,
82 				interrupt-parent = <&gpio>;
88 			reg = <3>;
89 			#address-cells = <1>;
90 			#size-cells = <0>;
92 			phy21: ethernet-phy@1 {
93 				reg = <1>;
94 				marvell,reg-init = <3 0x10 0 0x5777>,
98 				interrupt-parent = <&gpio>;
101 			phy22: ethernet-phy@2 {
102 				reg = <2>;
103 				marvell,reg-init = <3 0x10 0 0x5777>,
107 				interrupt-parent = <&gpio>;
110 			phy23: ethernet-phy@3 {
111 				reg = <3>;
112 				marvell,reg-init = <3 0x10 0 0x5777>,
116 				interrupt-parent = <&gpio>;
119 			phy24: ethernet-phy@4 {
120 				reg = <4>;
121 				marvell,reg-init = <3 0x10 0 0x5777>,
125 				interrupt-parent = <&gpio>;