Lines Matching +full:connected +full:- +full:positive
8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
26 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
28 - cell-index : 1 cell, hardware index of the EMAC cell on a given
31 - max-frame-size : 1 cell, maximum frame size supported in bytes
32 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
35 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
38 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
41 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
44 - phy-mode : string, mode of operations of the PHY interface.
48 - mdio-device : 1 cell, required iff using shared MDIO registers
51 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
53 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
55 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
58 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
61 EMAC, that is the content of the current (bogus) "phy-port"
65 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
67 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
68 for, used if phy-address is absent. bit 0x00000001 is
71 doesn't handle phy-address yet so for now, keep
73 - phy-handle : Used to describe configurations where a external PHY
76 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
78 rx-fifo-size). For Axon, either absent or 2048.
79 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
81 tx-fifo-size). For Axon, either absent or 2048.
82 - tah-device : 1 cell, optional. If connected to a TAH engine for
84 - tah-channel : 1 cell, optional. If appropriate, channel used on the
86 - fixed-link : Fixed-link subnode describing a link to a non-MDIO
88 Documentation/devicetree/bindings/net/fixed-link.txt
90 - mdio subnode : When the EMAC has a phy connected to its local
94 - #address-cells: Must be <1>.
95 - #size-cells: Must be <0>.
105 compatible = "ibm,emac-440gp", "ibm,emac";
106 interrupt-parent = <&UIC1>;
109 local-mac-address = [00 04 AC E3 1B 1E];
110 mal-device = <&MAL0>;
111 mal-tx-channel = <0 1>;
112 mal-rx-channel = <0>;
113 cell-index = <0>;
114 max-frame-size = <5dc>;
115 rx-fifo-size = <1000>;
116 tx-fifo-size = <800>;
117 phy-mode = "rmii";
118 phy-map = <00000001>;
119 zmii-device = <&ZMII0>;
120 zmii-channel = <0>;
125 compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
126 interrupt-parent = <&EMAC1>;
128 #interrupt-cells = <1>;
129 #address-cells = <0>;
130 #size-cells = <0>;
131 interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH /* Status */
134 local-mac-address = [000000000000]; /* Filled in by U-Boot */
135 mal-device = <&MAL0>;
136 mal-tx-channel = <0>;
137 mal-rx-channel = <0>;
138 cell-index = <0>;
139 max-frame-size = <9000>;
140 rx-fifo-size = <16384>;
141 tx-fifo-size = <2048>;
142 fifo-entry-size = <10>;
143 phy-mode = "rgmii";
144 phy-handle = <&phy0>;
145 phy-map = <0x00000000>;
146 rgmii-device = <&RGMII0>;
147 rgmii-channel = <0>;
148 tah-device = <&TAH0>;
149 tah-channel = <0>;
150 has-inverted-stacr-oc;
151 has-new-stacr-staopc;
154 #address-cells = <1>;
155 #size-cells = <0>;
157 phy0: ethernet-phy@0 {
158 compatible = "ethernet-phy-ieee802.3-c22";
168 - device_type : "dma-controller"
169 - compatible : compatible list, containing 2 entries, first is
170 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
173 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
174 - interrupts : <interrupt mapping for the MAL interrupts sources:
179 interrupts, all level positive sensitive: 10, 11, 32,
181 - dcr-reg : < DCR registers range >
182 - dcr-parent : if needed for dcr-reg
183 - num-tx-chans : 1 cell, number of Tx channels
184 - num-rx-chans : 1 cell, number of Rx channels
189 - compatible : compatible list, containing 2 entries, first is
190 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
193 - reg : <registers mapping>
198 - compatible : compatible list, containing 2 entries, first is
199 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
201 For Axon, "ibm,rgmii-axon","ibm,rgmii"
202 - reg : <registers mapping>
203 - revision : as provided by the RGMII new version register if