Lines Matching +full:imx93 +full:- +full:clock
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
23 - fsl,imx28-fec
24 - fsl,imx6q-fec
25 - fsl,mvf600-fec
26 - fsl,s32v234-fec
27 - items:
28 - enum:
29 - fsl,imx53-fec
30 - fsl,imx6sl-fec
31 - const: fsl,imx25-fec
32 - items:
33 - enum:
34 - fsl,imx35-fec
35 - fsl,imx51-fec
36 - const: fsl,imx27-fec
37 - items:
38 - enum:
39 - fsl,imx6ul-fec
40 - fsl,imx6sx-fec
41 - const: fsl,imx6q-fec
42 - items:
43 - enum:
44 - fsl,imx7d-fec
45 - const: fsl,imx6sx-fec
46 - items:
47 - const: fsl,imx8mq-fec
48 - const: fsl,imx6sx-fec
49 - items:
50 - enum:
51 - fsl,imx8mm-fec
52 - fsl,imx8mn-fec
53 - fsl,imx8mp-fec
54 - fsl,imx93-fec
55 - const: fsl,imx8mq-fec
56 - const: fsl,imx6sx-fec
57 - items:
58 - const: fsl,imx8qm-fec
59 - const: fsl,imx6sx-fec
60 - items:
61 - enum:
62 - fsl,imx8dxl-fec
63 - fsl,imx8qxp-fec
64 - const: fsl,imx8qm-fec
65 - const: fsl,imx6sx-fec
66 - items:
67 - enum:
68 - fsl,imx8ulp-fec
69 - const: fsl,imx6ul-fec
70 - const: fsl,imx6q-fec
79 interrupt-names:
81 - items:
82 - const: int0
83 - items:
84 - const: int0
85 - const: pps
86 - items:
87 - const: int0
88 - const: int1
89 - const: int2
90 - items:
91 - const: int0
92 - const: int1
93 - const: int2
94 - const: pps
101 The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock.
102 The "ptp"(option), for IEEE1588 timer clock that requires the clock.
103 The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like
104 RGMII TXC clock or RMII reference clock. It depends on board design,
105 the clock is required if RGMII TXC and RMII reference clock source from
107 The "enet_out"(option), output clock for external device, like supply clock
108 for PHY. The clock is required if PHY clock source from SOC.
109 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz.
110 The clock is required if SoC RGMII enable clock delay.
112 clock-names:
117 - ipg
118 - ahb
119 - ptp
120 - enet_clk_ref
121 - enet_out
122 - enet_2x_txclk
124 phy-mode: true
126 phy-handle: true
128 fixed-link: true
130 local-mac-address: true
132 mac-address: true
134 nvmem-cells: true
136 nvmem-cell-names: true
138 tx-internal-delay-ps:
141 rx-internal-delay-ps:
144 phy-supply:
148 power-domains:
151 fsl,num-tx-queues:
154 The property is valid for enet-avb IP, which supports hw multi queues.
158 fsl,num-rx-queues:
161 The property is valid for enet-avb IP, which supports hw multi queues.
165 fsl,magic-packet:
170 fsl,err006687-workaround-present:
176 fsl,stop-mode:
177 $ref: /schemas/types.yaml#/definitions/phandle-array
179 - items:
180 - description: phandle to general purpose register node
181 - description: the gpr register offset for ENET stop request
182 - description: the gpr bit offset for ENET stop request
193 # To avoid these, create a phy node according to ethernet-phy.yaml in the same
194 # directory, and point the FEC's "phy-handle" property to it. Then use
195 # the phy's reset binding, again described by ethernet-phy.yaml.
197 phy-reset-gpios:
202 phy-reset-duration:
207 "phy-reset-gpios" is available. Missing the property will have the
211 phy-reset-active-high:
216 "phy-reset-gpios" property is reversed (H=reset state, L=operation state).
218 phy-reset-post-delay:
222 Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay
223 milliseconds will be observed after the phy-reset-gpios has been toggled.
228 - compatible
229 - reg
230 - interrupts
239 - |
241 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
244 phy-mode = "mii";
245 phy-reset-gpios = <&gpio2 14 0>;
246 phy-supply = <®_fec_supply>;
250 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
253 phy-mode = "mii";
254 phy-reset-gpios = <&gpio2 14 0>;
255 phy-supply = <®_fec_supply>;
256 phy-handle = <ðphy0>;
259 #address-cells = <1>;
260 #size-cells = <0>;
262 ethphy0: ethernet-phy@0 {
263 compatible = "ethernet-phy-ieee802.3-c22";