Lines Matching +full:rx +full:- +full:delay +full:- +full:ps
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
28 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
32 - const: ethernet-phy-ieee802.3-c22
34 - const: ethernet-phy-ieee802.3-c45
36 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
46 - items:
47 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
48 - const: ethernet-phy-ieee802.3-c22
49 - items:
50 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
51 - const: ethernet-phy-ieee802.3-c45
62 max-speed:
64 - 10
65 - 100
66 - 1000
67 - 2500
68 - 5000
69 - 10000
70 - 20000
71 - 25000
72 - 40000
73 - 50000
74 - 56000
75 - 100000
76 - 200000
80 phy-10base-t1l-2.4vpp:
89 broken-turn-around:
102 enet-phy-lane-swap:
105 If set, indicates the PHY will swap the TX/RX lanes to
109 enet-phy-lane-no-swap:
113 TX/RX lanes. This property allows the PHY to work correctly after
117 eee-broken-100tx:
123 eee-broken-1000t:
129 eee-broken-10gt:
135 eee-broken-1000kx:
141 eee-broken-10gkx4:
147 eee-broken-10gkr:
154 $ref: /schemas/types.yaml#/definitions/phandle-array
159 phy-is-integrated:
171 reset-names:
174 reset-gpios:
179 reset-assert-us:
181 Delay after the reset was asserted in microseconds. If this
182 property is missing the delay will be skipped.
184 reset-deassert-us:
186 Delay after the reset was deasserted in microseconds. If
187 this property is missing the delay will be skipped.
194 rx-internal-delay-ps:
196 RGMII Receive PHY Clock Delay defined in pico seconds. This is used for
197 PHY's that have configurable RX internal delays. If this property is
198 present then the PHY applies the RX delay.
200 tx-internal-delay-ps:
202 RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for
204 present then the PHY applies the TX delay.
210 '#address-cells':
213 '#size-cells':
217 '^led@[a-f0-9]+$':
229 - reg
236 - reg
241 - |
242 #include <dt-bindings/leds/common.h>
245 #address-cells = <1>;
246 #size-cells = <0>;
248 ethernet-phy@0 {
249 compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45";
250 interrupt-parent = <&PIC>;
255 reset-names = "phy";
256 reset-gpios = <&gpio1 4 1>;
257 reset-assert-us = <1000>;
258 reset-deassert-us = <2000>;
261 #address-cells = <1>;
262 #size-cells = <0>;
268 default-state = "keep";