Lines Matching +full:rzn1 +full:- +full:a5psw
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clément Léger <clement.leger@bootlin.com>
17 - $ref: dsa.yaml#/$defs/ethernet-ports
22 - enum:
23 - renesas,r9a06g032-a5psw
24 - const: renesas,rzn1-a5psw
31 - description: Device Level Ring (DLR) interrupt
32 - description: Switch interrupt
33 - description: Parallel Redundancy Protocol (PRP) interrupt
34 - description: Integrated HUB module interrupt
35 - description: Receive Pattern Match interrupt
37 interrupt-names:
39 - const: dlr
40 - const: switch
41 - const: prp
42 - const: hub
43 - const: ptrn
45 power-domains:
54 - description: AHB clock used for the switch register interface
55 - description: Switch system clock
57 clock-names:
59 - const: hclk
60 - const: clk
62 ethernet-ports:
66 "^(ethernet-)?port@[0-4]$":
70 pcs-handle:
73 phandle pointing to a PCS sub-node compatible with
74 renesas,rzn1-miic.yaml#
79 - compatible
80 - reg
81 - clocks
82 - clock-names
83 - power-domains
86 - |
87 #include <dt-bindings/gpio/gpio.h>
88 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
89 #include <dt-bindings/interrupt-controller/arm-gic.h>
92 compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
95 clock-names = "hclk", "clk";
96 power-domains = <&sysctrl>;
102 interrupt-names = "dlr", "switch", "prp", "hub", "ptrn";
106 ethernet-ports {
107 #address-cells = <1>;
108 #size-cells = <0>;
113 phy-handle = <&switch0phy3>;
114 pcs-handle = <&mii_conv4>;
120 phy-handle = <&switch0phy1>;
121 pcs-handle = <&mii_conv3>;
127 phy-mode = "internal";
129 fixed-link {
131 full-duplex;
137 #address-cells = <1>;
138 #size-cells = <0>;
140 reset-gpios = <&gpio0a 2 GPIO_ACTIVE_HIGH>;
141 reset-delay-us = <15>;
142 clock-frequency = <2500000>;
144 switch0phy1: ethernet-phy@1{
148 switch0phy3: ethernet-phy@3{