Lines Matching +full:xrx200 +full:- +full:mdio

6 - compatible	: "lantiq,xrx200-gswip" for the embedded GSWIP in the
7 		  xRX200 SoC
8 		  "lantiq,xrx300-gswip" for the embedded GSWIP in the
10 		  "lantiq,xrx330-gswip" for the embedded GSWIP in the
12 - reg		: memory range of the GSWIP core registers
13 		: memory range of the GSWIP MDIO registers
20 Required properties for MDIO bus:
21 - compatible	: "lantiq,xrx200-mdio" for the MDIO bus inside the GSWIP
22 		  core of the xRX200 SoC and the PHYs connected to it.
24 See Documentation/devicetree/bindings/net/mdio.txt for a list of additional
29 - compatible	: "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw"
30 		  "lantiq,xrx300-gphy-fw", "lantiq,gphy-fw"
31 		  "lantiq,xrx330-gphy-fw", "lantiq,gphy-fw"
34 - lantiq,rcu	: reference to the rcu syscon
39 - reg		: Offset of the GPHY firmware register in the RCU
41 - resets	: list of resets of the embedded GPHY
42 - reset-names	: list of names of the resets
49 	#address-cells = <1>;
50 	#size-cells = <0>;
51 	compatible = "lantiq,xrx200-gswip";
53 		0xe10b100 0xd8		/* mdio */
59 		#address-cells = <1>;
60 		#size-cells = <0>;
65 			phy-mode = "rgmii";
66 			phy-handle = <&phy0>;
72 			phy-mode = "rgmii";
73 			phy-handle = <&phy1>;
79 			phy-mode = "internal";
80 			phy-handle = <&phy11>;
86 			phy-mode = "internal";
87 			phy-handle = <&phy13>;
93 			phy-mode = "rgmii";
94 			phy-handle = <&phy5>;
103 	mdio {
104 		#address-cells = <1>;
105 		#size-cells = <0>;
106 		compatible = "lantiq,xrx200-mdio";
109 		phy0: ethernet-phy@0 {
112 		phy1: ethernet-phy@1 {
115 		phy5: ethernet-phy@5 {
118 		phy11: ethernet-phy@11 {
121 		phy13: ethernet-phy@13 {
126 	gphy-fw {
127 		compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
129 		#address-cells = <1>;
130 		#size-cells = <0>;
136 			reset-names = "gphy";
143 			reset-names = "gphy";