Lines Matching +full:pll +full:- +full:mode

1 Atheros AR9331 built-in switch
4 It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal
5 MDIO bus. All PHYs are built-in as well.
9  - compatible: should be: "qca,ar9331-switch"
10  - reg: Address on the MII bus for the switch.
11  - resets : Must contain an entry for each entry in reset-names.
12  - reset-names : Must include the following entries: "switch"
13  - interrupt-parent: Phandle to the parent interrupt controller
14  - interrupts: IRQ line for the switch
15  - interrupt-controller: Indicates the switch is itself an interrupt
17  - #interrupt-cells: must be 1
18  - mdio: Container of PHY and devices on the switches MDIO bus.
25 	compatible = "qca,ar9330-eth";
30 	reset-names = "mac", "mdio";
31 	clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
32 	clock-names = "eth", "mdio";
34 	phy-mode = "mii";
35 	phy-handle = <&phy_port4>;
39 	compatible = "qca,ar9330-eth";
43 	reset-names = "mac", "mdio";
44 	clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
45 	clock-names = "eth", "mdio";
47 	phy-mode = "gmii";
49 	fixed-link {
51 		full-duplex;
55 		#address-cells = <1>;
56 		#size-cells = <0>;
59 			#address-cells = <1>;
60 			#size-cells = <0>;
62 			compatible = "qca,ar9331-switch";
65 			reset-names = "switch";
67 			interrupt-parent = <&miscintc>;
70 			interrupt-controller;
71 			#interrupt-cells = <1>;
74 				#address-cells = <1>;
75 				#size-cells = <0>;
81 					phy-mode = "gmii";
83 					fixed-link {
85 						full-duplex;
91 					phy-handle = <&phy_port0>;
92 					phy-mode = "internal";
97 					phy-handle = <&phy_port1>;
98 					phy-mode = "internal";
103 					phy-handle = <&phy_port2>;
104 					phy-mode = "internal";
109 					phy-handle = <&phy_port3>;
110 					phy-mode = "internal";
115 				#address-cells = <1>;
116 				#size-cells = <0>;
118 				interrupt-parent = <&switch10>;