Lines Matching +full:jz4780 +full:- +full:nand
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs NAND controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
14 - $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
21 - ingenic,jz4780-nand
25 - description: Bank number, offset and size of first attached NAND chip
26 - description: Bank number, offset and size of second attached NAND chip
27 - description: Bank number, offset and size of third attached NAND chip
28 - description: Bank number, offset and size of fourth attached NAND chip
31 ecc-engine: true
40 "^nand@[a-f0-9]$":
42 $ref: raw-nand-chip.yaml
45 rb-gpios:
49 wp-gpios:
50 description: GPIO specifier for the write-protect pin.
56 - compatible
57 - reg
62 - |
63 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
64 memory-controller@13410000 {
65 compatible = "ingenic,jz4780-nemc";
67 #address-cells = <2>;
68 #size-cells = <1>;
78 nand-controller@1 {
79 compatible = "ingenic,jz4780-nand";
82 #address-cells = <1>;
83 #size-cells = <0>;
85 ecc-engine = <&bch>;
87 ingenic,nemc-tAS = <10>;
88 ingenic,nemc-tAH = <5>;
89 ingenic,nemc-tBP = <10>;
90 ingenic,nemc-tAW = <15>;
91 ingenic,nemc-tSTRV = <100>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pins_nemc>;
96 nand@1 {
99 nand-ecc-step-size = <1024>;
100 nand-ecc-strength = <24>;
101 nand-ecc-mode = "hw";
102 nand-on-flash-bbt;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pins_nemc_cs1>;
108 compatible = "fixed-partitions";
109 #address-cells = <2>;
110 #size-cells = <2>;
113 label = "u-boot-spl";
118 label = "u-boot";
123 label = "u-boot-env";