Lines Matching +full:nand +full:- +full:controller

1 * Cadence NAND controller
4   - compatible : "cdns,hp-nfc"
5   - reg : Contains two entries, each of which is a tuple consisting of a
7 	  length of the controller register set. The second entry is the
9   - reg-names: should contain "reg" and "sdma"
10   - #address-cells: should be 1. The cell encodes the chip select connection.
11   - #size-cells : should be 0.
12   - interrupts : The interrupt number.
13   - clocks: phandle of the controller core clock (nf_clk).
16   - dmas: shall reference DMA channel associated to the NAND controller
17   - cdns,board-delay-ps : Estimated Board delay. The value includes the total
24 Child nodes represent the available NAND chips.
26 Required properties of NAND chips:
27   - reg: shall contain the native Chip Select ids from 0 to max supported by
28     the cadence nand flash controller
30 See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
35 nand_controller: nand-controller@60000000 {
36 	  compatible = "cdns,hp-nfc";
37 	  #address-cells = <1>;
38 	  #size-cells = <0>;
40 	  reg-names = "reg", "sdma";
42 	  cdns,board-delay-ps = <4830>;
44 	  nand@0 {
46 	      label = "nand-1";
48 	  nand@1 {
50 	      label = "nand-2";