Lines Matching +full:gcc +full:- +full:sm8350
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
19 - enum:
20 - qcom,sdhci-msm-v4
22 - items:
23 - enum:
24 - qcom,apq8084-sdhci
25 - qcom,ipq4019-sdhci
26 - qcom,ipq8074-sdhci
27 - qcom,msm8226-sdhci
28 - qcom,msm8953-sdhci
29 - qcom,msm8974-sdhci
30 - qcom,msm8976-sdhci
31 - qcom,msm8916-sdhci
32 - qcom,msm8992-sdhci
33 - qcom,msm8994-sdhci
34 - qcom,msm8996-sdhci
35 - qcom,msm8998-sdhci
36 - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
37 - items:
38 - enum:
39 - qcom,ipq5018-sdhci
40 - qcom,ipq5332-sdhci
41 - qcom,ipq6018-sdhci
42 - qcom,ipq9574-sdhci
43 - qcom,qcm2290-sdhci
44 - qcom,qcs404-sdhci
45 - qcom,qdu1000-sdhci
46 - qcom,sc7180-sdhci
47 - qcom,sc7280-sdhci
48 - qcom,sc8280xp-sdhci
49 - qcom,sdm630-sdhci
50 - qcom,sdm670-sdhci
51 - qcom,sdm845-sdhci
52 - qcom,sdx55-sdhci
53 - qcom,sdx65-sdhci
54 - qcom,sm6115-sdhci
55 - qcom,sm6125-sdhci
56 - qcom,sm6350-sdhci
57 - qcom,sm6375-sdhci
58 - qcom,sm8150-sdhci
59 - qcom,sm8250-sdhci
60 - qcom,sm8350-sdhci
61 - qcom,sm8450-sdhci
62 - qcom,sm8550-sdhci
63 - qcom,sm8650-sdhci
64 - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
70 reg-names:
77 - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
78 - description: SDC MMC clock, MCLK
79 - description: TCXO clock
80 - description: clock for Inline Crypto Engine
81 - description: SDCC bus voter clock
82 - description: reference clock for RCLK delay calibration
83 - description: sleep clock for RCLK delay calibration
85 clock-names:
88 - const: iface
89 - const: core
90 - const: xo
91 - enum: [ice, bus, cal, sleep]
92 - enum: [ice, bus, cal, sleep]
93 - enum: [ice, bus, cal, sleep]
94 - enum: [ice, bus, cal, sleep]
96 dma-coherent: true
101 interrupt-names:
103 - const: hc_irq
104 - const: pwr_irq
106 pinctrl-names:
109 - const: default
110 - const: sleep
112 pinctrl-0:
116 pinctrl-1:
123 qcom,ddr-config:
127 qcom,dll-config:
140 - description: data path, sdhc to ddr
141 - description: config path, cpu to sdhc
143 interconnect-names:
146 - const: sdhc-ddr
147 - const: cpu-sdhc
149 power-domains:
153 operating-points-v2: true
156 '^opp-table(-[a-z0-9]+)?$':
160 const: operating-points-v2
163 '^opp-?[0-9]+$':
165 - required-opps
168 - compatible
169 - reg
170 - clocks
171 - clock-names
172 - interrupts
175 - $ref: sdhci-common.yaml#
177 - if:
182 - qcom,sdhci-msm-v4
188 - description: Host controller register map
189 - description: SD Core register map
190 - description: CQE register map
191 - description: Inline Crypto Engine register map
192 reg-names:
195 - const: hc
196 - const: core
197 - const: cqhci
198 - const: ice
204 - description: Host controller register map
205 - description: CQE register map
206 - description: Inline Crypto Engine register map
207 reg-names:
210 - const: hc
211 - const: cqhci
212 - const: ice
217 - |
218 #include <dt-bindings/interrupt-controller/arm-gic.h>
219 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
220 #include <dt-bindings/clock/qcom,rpmh.h>
221 #include <dt-bindings/power/qcom,rpmhpd.h>
224 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
229 interrupt-names = "hc_irq", "pwr_irq";
231 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
232 <&gcc GCC_SDCC2_APPS_CLK>,
234 clock-names = "iface", "core", "xo";
236 qcom,dll-config = <0x0007642c>;
237 qcom,ddr-config = <0x80040868>;
238 power-domains = <&rpmhpd RPMHPD_CX>;
240 operating-points-v2 = <&sdhc2_opp_table>;
242 sdhc2_opp_table: opp-table {
243 compatible = "operating-points-v2";
245 opp-19200000 {
246 opp-hz = /bits/ 64 <19200000>;
247 required-opps = <&rpmhpd_opp_min_svs>;
250 opp-50000000 {
251 opp-hz = /bits/ 64 <50000000>;
252 required-opps = <&rpmhpd_opp_low_svs>;
255 opp-100000000 {
256 opp-hz = /bits/ 64 <100000000>;
257 required-opps = <&rpmhpd_opp_svs>;
260 opp-202000000 {
261 opp-hz = /bits/ 64 <202000000>;
262 required-opps = <&rpmhpd_opp_svs_l1>;