Lines Matching +full:gcc +full:- +full:msm8994
1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
19 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
20 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
21 "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"
22 "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
23 "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
24 "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
25 "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
26 "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
27 "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
28 "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
30 have the string "qcom,sdhci-msm-v4" without the SoC compatible string
33 - reg: Base address and length of the register in the following order:
34 - Host controller register map (required)
35 - SD Core register map (required for controllers earlier than msm-v5)
36 - CQE register map (Optional, CQE support is present on SDHC instance meant
38 - Inline Crypto Engine register map (optional)
39 - reg-names: When CQE register map is supplied, below reg-names are required
40 - "hc" for Host controller register map
41 - "core" for SD core register map
42 - "cqhci" for CQE register map
43 - "ice" for Inline Crypto Engine register map (optional)
44 - interrupts: Should contain an interrupt-specifiers for the interrupts:
45 - Host controller interrupt (required)
46 - pinctrl-names: Should contain only one value - "default".
47 - pinctrl-0: Should specify pin control groups used for this controller.
48 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
49 - clock-names: Should contain the following:
50 "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
51 "core" - SDC MMC clock (MCLK) (required)
52 "bus" - SDCC bus voter clock (optional)
53 "xo" - TCXO clock (optional)
54 "cal" - reference clock for RCLK delay calibration (optional)
55 "sleep" - sleep clock for RCLK delay calibration (optional)
56 "ice" - clock for Inline Crypto Engine (optional)
58 - qcom,ddr-config: Certain chipsets and platforms require particular settings
62 - qcom,dll-config: Chipset and Platform specific value. Use this field to
67 - interconnects: Pairs of phandles and interconnect provider specifier
71 - interconnect-names: For sdhc, we have two main paths.
75 is "sdhc-ddr" and for config interconnect path it is
76 "cpu-sdhc".
83 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
86 bus-width = <8>;
87 non-removable;
89 vmmc-supply = <&pm8941_l20>;
90 vqmmc-supply = <&pm8941_s3>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
95 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
96 clock-names = "core", "iface";
99 interconnect-names = "sdhc-ddr","cpu-sdhc";
101 qcom,dll-config = <0x000f642c>;
102 qcom,ddr-config = <0x80040868>;
106 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
109 bus-width = <4>;
110 cd-gpios = <&msmgpio 62 0x1>;
112 vmmc-supply = <&pm8941_l21>;
113 vqmmc-supply = <&pm8941_l13>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
118 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
119 clock-names = "core", "iface";
121 qcom,dll-config = <0x0007642c>;
122 qcom,ddr-config = <0x80040868>;