Lines Matching +full:tuning +full:- +full:step
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
20 - mediatek,mt6795-mmc
21 - mediatek,mt7620-mmc
22 - mediatek,mt7622-mmc
23 - mediatek,mt7986-mmc
24 - mediatek,mt7988-mmc
25 - mediatek,mt8135-mmc
26 - mediatek,mt8173-mmc
27 - mediatek,mt8183-mmc
28 - mediatek,mt8196-mmc
29 - mediatek,mt8516-mmc
30 - items:
31 - const: mediatek,mt7623-mmc
32 - const: mediatek,mt2701-mmc
33 - items:
34 - enum:
35 - mediatek,mt6893-mmc
36 - mediatek,mt8186-mmc
37 - mediatek,mt8188-mmc
38 - mediatek,mt8192-mmc
39 - mediatek,mt8195-mmc
40 - mediatek,mt8365-mmc
41 - const: mediatek,mt8183-mmc
46 - description: base register (required).
47 - description: top base register (required for MT8183).
55 clock-names:
61 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
66 interrupt-names:
68 - const: msdc
69 - const: sdio_wakeup
71 pinctrl-names:
73 Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
78 - const: default
79 - const: state_uhs
80 - const: state_eint
82 pinctrl-0:
87 pinctrl-1:
92 pinctrl-2:
97 hs400-ds-delay:
104 mediatek,hs200-cmd-int-delay:
113 mediatek,hs400-cmd-int-delay:
122 mediatek,hs400-cmd-resp-sel-rising:
129 mediatek,hs400-ds-dly3:
134 For different corner IC, the time is different about one step, it is
141 mediatek,latch-ck:
144 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
147 applied to compatible "mediatek,mt2701-mmc".
151 mediatek,tuning-step:
154 Some SoCs need extend tuning step for better delay value to avoid CRC issue.
155 If not present, default tuning step is 32. For eMMC and SD, this can yield
163 reset-names:
167 - compatible
168 - reg
169 - interrupts
170 - clocks
171 - clock-names
172 - pinctrl-names
173 - pinctrl-0
174 - pinctrl-1
175 - vmmc-supply
176 - vqmmc-supply
179 - $ref: mmc-controller.yaml#
180 - if:
184 - mediatek,mt2701-mmc
185 - mediatek,mt6779-mmc
186 - mediatek,mt6795-mmc
187 - mediatek,mt7620-mmc
188 - mediatek,mt7622-mmc
189 - mediatek,mt7623-mmc
190 - mediatek,mt8135-mmc
191 - mediatek,mt8173-mmc
192 - mediatek,mt8183-mmc
193 - mediatek,mt8186-mmc
194 - mediatek,mt8188-mmc
195 - mediatek,mt8195-mmc
196 - mediatek,mt8196-mmc
197 - mediatek,mt8516-mmc
203 - description: source clock
204 - description: HCLK which used for host
205 - description: independent source clock gate
206 clock-names:
209 - const: source
210 - const: hclk
211 - const: source_cg
213 - if:
217 const: mediatek,mt2712-mmc
223 - description: source clock
224 - description: HCLK which used for host
225 - description: independent source clock gate
226 - description: bus clock used for internal register access (required for MSDC0/3).
227 clock-names:
230 - const: source
231 - const: hclk
232 - const: source_cg
233 - const: bus_clk
235 - if:
240 - mediatek,mt7986-mmc
241 - mediatek,mt7988-mmc
242 - mediatek,mt8183-mmc
243 - mediatek,mt8196-mmc
253 - if:
258 - mediatek,mt7986-mmc
264 - description: source clock
265 - description: HCLK which used for host
266 - description: independent source clock gate
267 - description: bus clock used for internal register access (required for MSDC0/3).
268 - description: msdc subsys clock gate
269 clock-names:
272 - const: source
273 - const: hclk
274 - const: source_cg
275 - const: bus_clk
276 - const: sys_cg
278 - if:
283 - mediatek,mt7988-mmc
288 - description: source clock
289 - description: HCLK which used for host
290 - description: Advanced eXtensible Interface
291 - description: Advanced High-performance Bus clock
292 clock-names:
294 - const: source
295 - const: hclk
296 - const: axi_cg
297 - const: ahb_cg
299 - if:
303 - mediatek,mt6893-mmc
304 - mediatek,mt8186-mmc
305 - mediatek,mt8188-mmc
306 - mediatek,mt8195-mmc
311 - description: source clock
312 - description: HCLK which used for host
313 - description: independent source clock gate
314 - description: crypto clock used for data encrypt/decrypt (optional)
315 clock-names:
317 - const: source
318 - const: hclk
319 - const: source_cg
320 - const: crypto
322 - if:
326 const: mediatek,mt8192-mmc
331 - description: source clock
332 - description: HCLK which used for host
333 - description: independent source clock gate
334 - description: msdc subsys clock gate
335 - description: peripheral bus clock gate
336 - description: AXI bus clock gate
337 - description: AHB bus clock gate
338 clock-names:
340 - const: source
341 - const: hclk
342 - const: source_cg
343 - const: sys_cg
344 - const: pclk_cg
345 - const: axi_cg
346 - const: ahb_cg
351 - |
352 #include <dt-bindings/interrupt-controller/irq.h>
353 #include <dt-bindings/interrupt-controller/arm-gic.h>
354 #include <dt-bindings/clock/mt8173-clk.h>
356 compatible = "mediatek,mt8173-mmc";
359 vmmc-supply = <&mt6397_vemc_3v3_reg>;
360 vqmmc-supply = <&mt6397_vio18_reg>;
363 clock-names = "source", "hclk";
364 pinctrl-names = "default", "state_uhs";
365 pinctrl-0 = <&mmc0_pins_default>;
366 pinctrl-1 = <&mmc0_pins_uhs>;
367 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
368 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
369 hs400-ds-delay = <0x14015>;
370 mediatek,hs200-cmd-int-delay = <26>;
371 mediatek,hs400-cmd-int-delay = <14>;
372 mediatek,hs400-cmd-resp-sel-rising;
376 compatible = "mediatek,mt8173-mmc";
378 clock-names = "source", "hclk";
381 interrupt-names = "msdc", "sdio_wakeup";
382 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
384 pinctrl-names = "default", "state_uhs", "state_eint";
385 pinctrl-0 = <&mmc2_pins_default>;
386 pinctrl-1 = <&mmc2_pins_uhs>;
387 pinctrl-2 = <&mmc2_pins_eint>;
388 bus-width = <4>;
389 max-frequency = <200000000>;
390 cap-sd-highspeed;
391 sd-uhs-sdr104;
392 keep-power-in-suspend;
393 wakeup-source;
394 cap-sdio-irq;
395 no-mmc;
396 no-sd;
397 non-removable;
398 vmmc-supply = <&sdio_fixed_3v3>;
399 vqmmc-supply = <&mt6397_vgp3_reg>;
400 mmc-pwrseq = <&wifi_pwrseq>;