Lines Matching +full:mt2701 +full:- +full:mmc
1 * MTK MMC controller
3 The MTK MSDC can act as a MMC controller
4 to support MMC, SD, and SDIO types of memory cards.
6 This file documents differences between the core properties in mmc.txt
10 - compatible: value should be either of the following.
11 "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
12 "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
13 "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
14 "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
15 "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
16 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
17 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
18 "mediatek,mt7622-mmc": for MT7622 SoC
19 "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
20 "mediatek,mt7620-mmc", for MT7621 SoC (and others)
22 - reg: physical base address of the controller and length
23 - interrupts: Should contain MSDC interrupt number
24 - clocks: Should contain phandle for the clock feeding the MMC controller
25 - clock-names: Should contain the following:
26 "source" - source clock (required)
27 "hclk" - HCLK which used for host (required)
28 "source_cg" - independent source clock gate (required for MT2712)
29 "bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
30 - pinctrl-names: should be "default", "state_uhs"
31 - pinctrl-0: should contain default/high speed pin ctrl
32 - pinctrl-1: should contain uhs mode pin ctrl
33 - vmmc-supply: power to the Core
34 - vqmmc-supply: power to the IO
37 - assigned-clocks: PLL of the source clock
38 - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
39 - hs400-ds-delay: HS400 DS delay setting
40 - mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
43 - mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
46 - mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
49 - mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data c…
52 applied to compatible "mediatek,mt2701-mmc".
53 - resets: Phandle and reset specifier pair to softreset line of MSDC IP.
54 - reset-names: Should be "hrst".
57 mmc0: mmc@11230000 {
58 compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
61 vmmc-supply = <&mt6397_vemc_3v3_reg>;
62 vqmmc-supply = <&mt6397_vio18_reg>;
65 clock-names = "source", "hclk";
66 pinctrl-names = "default", "state_uhs";
67 pinctrl-0 = <&mmc0_pins_default>;
68 pinctrl-1 = <&mmc0_pins_uhs>;
69 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
70 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
71 hs400-ds-delay = <0x14015>;
72 mediatek,hs200-cmd-int-delay = <26>;
73 mediatek,hs400-cmd-int-delay = <14>;
74 mediatek,hs400-cmd-resp-sel-rising;