Lines Matching +full:mpc8378 +full:- +full:esdhc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl,esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC)
14 - Frank Li <Frank.Li@nxp.com>
19 - enum:
20 - fsl,mpc8536-esdhc
21 - fsl,mpc8378-esdhc
22 - fsl,p2020-esdhc
23 - fsl,p4080-esdhc
24 - fsl,t1040-esdhc
25 - fsl,t4240-esdhc
26 - fsl,ls1012a-esdhc
27 - fsl,ls1028a-esdhc
28 - fsl,ls1088a-esdhc
29 - fsl,ls1043a-esdhc
30 - fsl,ls1046a-esdhc
31 - fsl,ls2080a-esdhc
32 - const: fsl,esdhc
43 clock-frequency:
45 description: specifies eSDHC base clock frequency.
47 sdhci,wp-inverted:
51 specifies that eSDHC controller reports
52 inverted write-protect state; New devices should use the generic
53 "wp-inverted" property.
55 sdhci,1-bit-only:
60 1-bit data transfers. New devices should use the generic
61 "bus-width = <1>" property.
63 sdhci,auto-cmd12:
68 voltage-ranges:
69 $ref: /schemas/types.yaml#/definitions/uint32-matrix
72 - description: specifies minimum slot voltage (mV).
73 - description: specifies maximum slot voltage (mV).
77 dma-coherent: true
79 little-endian:
82 If the host controller is little-endian mode, specify
83 this property. The default endian mode is big-endian.
86 - compatible
87 - reg
88 - interrupts
91 - $ref: sdhci-common.yaml#
96 - |
98 compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
101 interrupt-parent = <&ipic>;
102 /* Filled in by U-Boot */
103 clock-frequency = <100000000>;
104 voltage-ranges = <3300 3300>;